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| author | Jan Stolarek <jan.stolarek@p.lodz.pl> | 2014-11-05 13:44:32 +0100 |
|---|---|---|
| committer | Jan Stolarek <jan.stolarek@p.lodz.pl> | 2014-11-06 12:50:17 +0100 |
| commit | 303776ab1ff8e192fe42374c8547b7c77305796e (patch) | |
| tree | de746f96f728081173fe4ad1b68e4d88a7936910 /compiler/cmm/CmmCallConv.hs | |
| parent | c0a235424a7a1963dddef6101da4edd3321b0002 (diff) | |
| download | haskell-303776ab1ff8e192fe42374c8547b7c77305796e.tar.gz | |
Update User's Guide, cleanup DynFlags
Diffstat (limited to 'compiler/cmm/CmmCallConv.hs')
| -rw-r--r-- | compiler/cmm/CmmCallConv.hs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/compiler/cmm/CmmCallConv.hs b/compiler/cmm/CmmCallConv.hs index f36fc0bae5..440ee5634f 100644 --- a/compiler/cmm/CmmCallConv.hs +++ b/compiler/cmm/CmmCallConv.hs @@ -106,7 +106,7 @@ passFloatArgsInXmm dflags = case platformArch (targetPlatform dflags) of -- On X86_64, we always pass 128-bit-wide vectors in registers. On 32-bit X86 -- and for all larger vector sizes on X86_64, LLVM's GHC calling convention --- doesn't currently passing vectors in registers. The patch to update the GHC +-- does not currently pass vectors in registers. The patch to update the GHC -- calling convention to support passing SIMD vectors in registers is small and -- well-contained, so it may make it into LLVM 3.4. The hidden -- -fllvm-pass-vectors-in-regs flag will generate LLVM code that attempts to |