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| author | Peter Trommler <ptrommler@acm.org> | 2015-11-11 12:32:19 +0100 |
|---|---|---|
| committer | Ben Gamari <ben@smart-cactus.org> | 2015-11-11 12:32:33 +0100 |
| commit | fb0d5120d383324c6934144b938525378e3ade75 (patch) | |
| tree | b01c3b34f7b342efcd471c0d5a5db75fe9d3eae2 /compiler/nativeGen/PPC/Ppr.hs | |
| parent | badf5d54907a5a5e9224c44310f991a52379b4c1 (diff) | |
| download | haskell-fb0d5120d383324c6934144b938525378e3ade75.tar.gz | |
nativeGen.PPC: Fix shift arith. right > 31 bits
Arithmetic right shifts of more than 31 bits set all bits to
the sign bit on PowerPC. iThe assembler does not allow shift
amounts larger than 32 so do an arithemetic right shift of 31
bit instead.
Fixes #10870
Test Plan: validate (especially on powerpc)
Reviewers: austin, erikd, bgamari
Reviewed By: bgamari
Subscribers: thomie
Differential Revision: https://phabricator.haskell.org/D1459
GHC Trac Issues: #10870
Diffstat (limited to 'compiler/nativeGen/PPC/Ppr.hs')
| -rw-r--r-- | compiler/nativeGen/PPC/Ppr.hs | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/compiler/nativeGen/PPC/Ppr.hs b/compiler/nativeGen/PPC/Ppr.hs index e5147794ce..99f9ab77ea 100644 --- a/compiler/nativeGen/PPC/Ppr.hs +++ b/compiler/nativeGen/PPC/Ppr.hs @@ -718,12 +718,17 @@ pprInstr (SR II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = pprInstr (XOR reg1 reg2 (RIReg reg2)) pprInstr (SL II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = - -- As aboce for SR, but for left shifts. + -- As above for SR, but for left shifts. -- Fixes ticket http://ghc.haskell.org/trac/ghc/ticket/10870 pprInstr (XOR reg1 reg2 (RIReg reg2)) -pprInstr (SRA II32 reg1 reg2 (RIImm (ImmInt i))) | i < 0 || i > 31 = - pprInstr (XOR reg1 reg2 (RIReg reg2)) +pprInstr (SRA II32 reg1 reg2 (RIImm (ImmInt i))) | i > 31 = + -- PT: I don't know what to do for negative shift amounts: + -- For now just panic. + -- + -- For shift amounts greater than 31 set all bit to the + -- value of the sign bit, this also what sraw does. + pprInstr (SRA II32 reg1 reg2 (RIImm (ImmInt 31))) pprInstr (SL fmt reg1 reg2 ri) = let op = case fmt of |