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* Mark eepromer and eeprom as deprecated.khali2015-07-071-0/+3
* decode-dimms: Manufacturer name changes from JEP106AQkhali2015-06-291-0/+1
* decode-dimms: Correctly check for out-of-bounds vendor IDkhali2015-06-291-0/+1
* py-smbus: Add support for python 3khali2015-01-261-0/+1
* Mention the current maintainer. Original patch from Wolfram Sang.khali2015-01-191-0/+1
* decode-dimms: Fix DDR3 extended temp range refresh rate decodingkhali2014-06-191-0/+1
* Manual pages for eeprog, eeprom and eepromer, contributed by Jaromirkhali2013-10-161-0/+3
* Add manual pages for decode-dimms and decode-vaiokhali2013-10-051-0/+2
* decode-dimms: Generate XHTML 1.1 compliant markupkhali2013-06-071-1/+1
* decode-dimms: Generate HTML 4.01 compliant markupkhali2013-06-071-0/+1
* py-smbus: fix module level docskhali2013-05-221-0/+1
* decode-dimms: Encode "degrees" to HTML degree symbolkhali2013-04-191-0/+1
* DDR3: Fully decode the SDRAM Device Type field.khali2013-04-151-0/+1
* DDR3: Add support for Load Reduced DIMM (LRDIMM).khali2013-04-151-0/+1
* DDR3: Don't print raw SSTE32882 register values. Undecoded, they havekhali2013-04-151-0/+1
* DDR3: Print physical characteristics and registered DIMM informationkhali2013-04-141-0/+1
* DDR3: Print width of all known module types.khali2013-04-141-0/+1
* DDR3: Decode and print reference card revision.khali2013-04-141-0/+1
* DDR3: Print timings at standard speeds. This makes it easier to figurekhali2013-04-141-1/+1
* DDR3: Fix speed and PC3 number of high-speed modules.khali2013-04-131-0/+1
* DDR3: Decode the FTB fields of tCk, tAA, tRCD, tRP and tRC.khali2013-04-131-0/+1
* DDR3: Don't print the medium and fine time bases, they aren't directlykhali2013-04-131-0/+1
* DDR3: Round down PC3 numbers to comply with Jedec.khali2013-04-131-0/+1
* DDR3: Round core timings up, not down.khali2013-04-131-0/+1
* DDR3: Use the right nibble from byte 21 as the MSB of tRAS.khali2013-04-131-0/+1
* Fix build error (NULL undefined) caused by missing include filegroeck2013-03-021-0/+1
* Decode more DDR3 module typeskhali2013-02-131-0/+1
* Prevent hang on reserved DDR3 module typekhali2013-02-131-0/+1
* Update CHANGES to reflect tools build fixgroeck2012-12-211-0/+1
* i2cdetect: Clarify the SMBus commands used for probing by default.khali2012-12-201-0/+1
* Print timings at standard PC speeds. The minimum cycle times for thekhali2012-12-201-1/+1
* Fix decoding of SDR SPD revision. The encoding changed with revisionkhali2012-12-201-0/+1
* Add section headers for SDR modules, to make the output easier to read.khali2012-12-201-0/+1
* Remove duplicate "ns" in SDR timings.khali2012-12-201-0/+1
* Strip former manufacturer name in side-by-side output mode, to avoidkhali2012-12-201-0/+1
* If DDR3 manufacturer page count parity is wrong, still print thekhali2012-12-201-0/+1
* Add manufacturer names from Jedec document JEP106AJ.khali2012-12-201-0/+1
* Print timings at standard DDR speeds. The minimum cycle times for thekhali2012-12-201-1/+1
* Print timings at standard DDR2 speeds. The minimum cycle times for thekhali2012-12-201-0/+1
* Missed update.khali2012-10-251-1/+1
* decode-dimms: Print only the DDR2 timings which were properly defined.khali2012-10-251-0/+1
* decode-dimms: Print DDR2 equivalent speed of tCK max.khali2012-10-251-0/+1
* decode-dimms: Print DDR core timings for all supported CAS values.khali2012-10-251-0/+1
* decode-dimms: Print extra timing values for DDR memory modules as we dokhali2012-10-251-0/+1
* decode-dimms: Default to merging cells in side-by-side output mode.khali2012-10-251-0/+1
* Don't let missing DDR2 SPD revision or PLL relock time break side-by-side out...khali2012-10-221-1/+1
* Print the number of banks, rows, columns and ranks for DDR modules askhali2012-10-211-0/+1
* Don't let missing DDR module height break side-by-side output.khali2012-10-211-1/+2
* In side-by-side merged cells mode, don't make columns larger than theykhali2012-09-071-0/+1
* If either SMBus Quick Write or SMBus Receive Byte command is missing,khali2012-09-071-0/+1