diff options
| -rw-r--r-- | src/atomic_ops/sysdeps/gcc/mips.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h index 73ca551..e5b8a5a 100644 --- a/src/atomic_ops/sysdeps/gcc/mips.h +++ b/src/atomic_ops/sysdeps/gcc/mips.h @@ -17,8 +17,6 @@ * consistent. This is really aimed at modern embedded implementations. */ -#include "../all_aligned_atomic_load_store.h" - #include "../test_and_set_t_is_ao_t.h" /* Data dependence does not imply read ordering. */ @@ -35,6 +33,19 @@ # define AO_T_IS_INT #endif +/* #include "../standard_ao_double_t.h" */ +/* TODO: Implement double-wide operations if available. */ + +#if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9) \ + || __clang_major__ > 3 \ + || (__clang_major__ == 3 && __clang_minor__ >= 5)) \ + && !defined(AO_DISABLE_GCC_ATOMICS) + /* Probably, it could be enabled even for earlier gcc/clang versions. */ +# include "generic.h" +#else + +#include "../all_aligned_atomic_load_store.h" + #ifdef AO_ICE9A1_LLSC_WAR /* ICE9 rev A1 chip (used in very few systems) is reported to */ /* have a low-frequency bug that causes LL to fail. */ @@ -168,8 +179,7 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) } #define AO_HAVE_fetch_compare_and_swap -/* #include "../standard_ao_double_t.h" */ -/* TODO: Implement double-wide operations if available. */ +#endif /* AO_DISABLE_GCC_ATOMICS */ /* CAS primitives with acquire, release and full semantics are */ /* generated automatically (and AO_int_... primitives are */ |