Add ARMv8/AArch32 Crypto Extension implemenation of SHA-256

* cipher/Makefile.am: Add 'sha256-armv8-aarch32-ce.S'.
* cipher/sha256-armv8-aarch32-ce.S: New.
* cipher/sha256.c (USE_ARM_CE): New.
(sha256_init, sha224_init): Check features for HWF_ARM_SHA1.
[USE_ARM_CE] (_gcry_sha256_transform_armv8_ce): New.
(transform) [USE_ARM_CE]: Use ARMv8 CE implementation if HW supports.
(SHA256_CONTEXT): Add 'use_arm_ce'.
* configure.ac: Add 'sha256-armv8-aarch32-ce.lo'.
--

Benchmark on Cortex-A53 (1152 Mhz):

Before:

                 |  nanosecs/byte   mebibytes/sec   cycles/byte
  SHA256         |     17.38 ns/B     54.88 MiB/s     20.02 c/B

After (~9.3x faster):

                 |  nanosecs/byte   mebibytes/sec   cycles/byte
  SHA256         |      1.85 ns/B     515.7 MiB/s      2.13 c/B

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi>

1 files changed, 30 insertions, 0 deletions

diff --git a/cipher/sha256.c b/cipher/sha256.c
index 1b82ee76..72818ceb 100644
--- a/cipher/sha256.c
+++ b/cipher/sha256.c
@@ -75,6 +75,17 @@
 # define USE_AVX2 1
 #endif
 
+/* USE_ARM_CE indicates whether to enable ARMv8 Crypto Extension assembly
+ * code. */
+#undef USE_ARM_CE
+#ifdef ENABLE_ARM_CRYPTO_SUPPORT
+# if defined(HAVE_ARM_ARCH_V6) && defined(__ARMEL__) \
+     && defined(HAVE_COMPATIBLE_GCC_ARM_PLATFORM_AS) \
+     && defined(HAVE_GCC_INLINE_ASM_AARCH32_CRYPTO)
+#  define USE_ARM_CE 1
+# endif
+#endif
+
 
 typedef struct {
   gcry_md_block_ctx_t bctx;
@@ -88,6 +99,9 @@ typedef struct {
 #ifdef USE_AVX2
   unsigned int use_avx2:1;
 #endif
+#ifdef USE_ARM_CE
+  unsigned int use_arm_ce:1;
+#endif
 } SHA256_CONTEXT;
 
 
@@ -129,6 +143,9 @@ sha256_init (void *context, unsigned int flags)
 #ifdef USE_AVX2
   hd->use_avx2 = (features & HWF_INTEL_AVX2) && (features & HWF_INTEL_BMI2);
 #endif
+#ifdef USE_ARM_CE
+  hd->use_arm_ce = (features & HWF_ARM_SHA2) != 0;
+#endif
   (void)features;
 }
 
@@ -167,6 +184,9 @@ sha224_init (void *context, unsigned int flags)
 #ifdef USE_AVX2
   hd->use_avx2 = (features & HWF_INTEL_AVX2) && (features & HWF_INTEL_BMI2);
 #endif
+#ifdef USE_ARM_CE
+  hd->use_arm_ce = (features & HWF_ARM_SHA2) != 0;
+#endif
   (void)features;
 }
 
@@ -355,6 +375,11 @@ unsigned int _gcry_sha256_transform_amd64_avx2(const void *input_data,
                                                size_t num_blks) ASM_FUNC_ABI;
 #endif
 
+#ifdef USE_ARM_CE
+unsigned int _gcry_sha256_transform_armv8_ce(u32 state[8],
+                                             const void *input_data,
+                                             size_t num_blks);
+#endif
 
 static unsigned int
 transform (void *ctx, const unsigned char *data, size_t nblks)
@@ -380,6 +405,11 @@ transform (void *ctx, const unsigned char *data, size_t nblks)
            + 4 * sizeof(void*) + ASM_EXTRA_STACK;
 #endif
 
+#ifdef USE_ARM_CE
+  if (hd->use_arm_ce)
+    return _gcry_sha256_transform_armv8_ce (&hd->h0, data, nblks);
+#endif
+
   do
     {
       burn = transform_blk (hd, data);