Spelling fixes in docs and comments.

--

GnuPG-bug-id: 3120
Reported-by: ka7 (klemens)
Signed-off-by: NIIBE Yutaka <gniibe@fsij.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/mpi/alpha/README b/mpi/alpha/README
index 55c0a291..00addfd3 100644
--- a/mpi/alpha/README
+++ b/mpi/alpha/README
@@ -5,7 +5,7 @@ RELEVANT OPTIMIZATION ISSUES
 EV4
 
 1. This chip has very limited store bandwidth.  The on-chip L1 cache is
-write-through, and a cache line is transfered from the store buffer to the
+write-through, and a cache line is transferred from the store buffer to the
 off-chip L2 in as much 15 cycles on most systems.  This delay hurts
 mpn_add_n, mpn_sub_n, mpn_lshift, and mpn_rshift.
 
@@ -20,7 +20,7 @@ EV5
 
 1. The memory bandwidth of this chip seems excellent, both for loads and
 stores.  Even when the working set is larger than the on-chip L1 and L2
-caches, the perfromance remain almost unaffected.
+caches, the performance remain almost unaffected.
 
 2. mulq has a measured latency of 13 cycles and an issue rate of 1 each 8th
 cycle.  umulh has a measured latency of 15 cycles and an issue rate of 1