diff options
| author | Haihao Xiang <haihao.xiang@intel.com> | 2018-07-20 14:05:51 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2018-08-13 10:55:05 +0800 |
| commit | fd79f756ce01432122cf2e9463fc8fe86f894449 (patch) | |
| tree | eb9d0e406859cbdb4596529fffb278aaf06e4f89 | |
| parent | 5693f1aa1539b2f14c5fa3b87e5446fa680a2361 (diff) | |
| download | libva-intel-driver-fd79f756ce01432122cf2e9463fc8fe86f894449.tar.gz | |
Change the sequence of reading MMIO registers
Signed-off-by: Haihao Xiang <haihao.xiang@intel.com>
| -rw-r--r-- | src/i965_encoder_vp8.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/i965_encoder_vp8.c b/src/i965_encoder_vp8.c index 0d6a2c86..7f940f8c 100644 --- a/src/i965_encoder_vp8.c +++ b/src/i965_encoder_vp8.c @@ -1367,12 +1367,6 @@ i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx, mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET; gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); - if (ipass == 0) { - mi_store_register_mem_param.offset = sizeof(unsigned int) * 4; - mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET; - gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); - } - mi_store_register_mem_param.offset = sizeof(unsigned int) * 5; mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_DQ_INDEX_REG_OFFSET; gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); @@ -1381,6 +1375,12 @@ i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx, mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_D_LOOP_FILTER_REG_OFFSET; gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); + if (ipass == 0) { + mi_store_register_mem_param.offset = sizeof(unsigned int) * 4; + mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET; + gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); + } + mi_store_register_mem_param.offset = sizeof(unsigned int) * 9; mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET; gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param); |