diff options
Diffstat (limited to 'src/shaders/post_processing/gen8')
| -rw-r--r-- | src/shaders/post_processing/gen8/Makefile.am | 27 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_bgrx.g8b | 21 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_bgrx.gxa | 87 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_pl2_8bit.g8b | 18 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_pl2_8bit.gxa | 96 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_pl3_8bit.g8b | 20 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_pl3_8bit.gxa | 109 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_rgbx.g8b | 21 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_rgbx.gxa | 87 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_uyvy.g8b | 16 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_uyvy.gxa | 84 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_yuy2.g8b | 16 | ||||
| -rw-r--r-- | src/shaders/post_processing/gen8/clear_yuy2.gxa | 84 |
13 files changed, 3 insertions, 683 deletions
diff --git a/src/shaders/post_processing/gen8/Makefile.am b/src/shaders/post_processing/gen8/Makefile.am index dfa7d31e..131e0fcf 100644 --- a/src/shaders/post_processing/gen8/Makefile.am +++ b/src/shaders/post_processing/gen8/Makefile.am @@ -19,15 +19,6 @@ INTEL_PP_PRE_G8B = \ conv_nv12.g8b \ conv_8bit_420_rgb32.g8b -INTEL_PP2_G8B = \ - clear_bgrx.g8b \ - clear_pl2_8bit.g8b \ - clear_pl3_8bit.g8b \ - clear_rgbx.g8b \ - clear_yuy2.g8b \ - clear_uyvy.g8b \ - $(NULL) - INTEL_PP_G8A = \ EOT.g8a \ PL2_AVS_Buf_0.g8a \ @@ -61,12 +52,9 @@ INTEL_PP_G8A = \ INTEL_PP_ASM = $(INTEL_PP_G8B:%.g8b=%.asm) INTEL_PP_GEN8_ASM = $(INTEL_PP_G8B:%.g8b=%.g8s) -INTEL_PP2_GXA = $(INTEL_PP2_G8B:%.g8b=%.gxa) -INTEL_PP2_GXS = $(INTEL_PP2_G8B:%.gxa=%.gxs) - TARGETS = if HAVE_GEN4ASM -TARGETS += $(INTEL_PP_G8B) $(INTEL_PP2_G8B) +TARGETS += $(INTEL_PP_G8B) endif all-local: $(TARGETS) @@ -81,16 +69,9 @@ $(INTEL_PP_GEN8_ASM): $(INTEL_PP_ASM) $(INTEL_PP_G8A) rm _pp0.$@ .g8s.g8b: $(AM_V_GEN)$(GEN4ASM) -a -o $@ -g 8 $< - -.gxa.gxs: - $(AM_V_GEN)cpp -P $< > _tmp.$@ && \ - m4 _tmp.$@ > $@ && \ - rm _tmp.$@ -.gxs.g8b: - $(AM_V_GEN)$(GEN4ASM) -o $@ -g 8 $< endif -CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM) $(INTEL_PP2_GXS) +CLEANFILES = $(INTEL_PP_GEN7_ASM) $(INTEL_PP_GEN8_ASM) DISTCLEANFILES = $(TARGETS) @@ -98,9 +79,7 @@ EXTRA_DIST = \ $(INTEL_PP_ASM) \ $(INTEL_PP_G8A) \ $(INTEL_PP_G8B) \ - $(INTEL_PP_PRE_G8B) \ - $(INTEL_PP2_G8B) \ - $(NULL) + $(INTEL_PP_PRE_G8B) # Extra clean files so that maintainer-clean removes *everything* MAINTAINERCLEANFILES = Makefile.in diff --git a/src/shaders/post_processing/gen8/clear_bgrx.g8b b/src/shaders/post_processing/gen8/clear_bgrx.g8b deleted file mode 100644 index e88addb7..00000000 --- a/src/shaders/post_processing/gen8/clear_bgrx.g8b +++ /dev/null @@ -1,21 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_bgrx.gxa b/src/shaders/post_processing/gen8/clear_bgrx.gxa deleted file mode 100644 index 0e2e4067..00000000 --- a/src/shaders/post_processing/gen8/clear_bgrx.gxa +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Red */ -define(`R', `g1.2<0,1,0>UB') -/* Green */ -define(`G', `g1.1<0,1,0>UB') -/* Blue */ -define(`B', `g1.0<0,1,0>UB') - -define(`BGRX_BTI', `1') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* RGBA/RGBX */ -shl(1) g16.0<1>UD ORIGX 6:w {align1}; -shl(1) g16.4<1>UD ORIGY 4:w {align1}; - -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(1) g17.3<1>UB ALPHA {align1}; -mov(1) g17.2<1>UB B {align1}; -mov(1) g17.1<1>UB G {align1}; -mov(1) g17.0<1>UB R {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b b/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b deleted file mode 100644 index 534c02ba..00000000 --- a/src/shaders/post_processing/gen8/clear_pl2_8bit.g8b +++ /dev/null @@ -1,18 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00040004 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, - { 0x00000001, 0x22080608, 0x00000000, 0x0007000f }, - { 0x00200001, 0x22201248, 0x00000020, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x0a0a8002 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa b/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa deleted file mode 100644 index ece0eb80..00000000 --- a/src/shaders/post_processing/gen8/clear_pl2_8bit.gxa +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Y */ -define(`Y', `g1.2<0,1,0>UB') -/* V */ -define(`CR', `g1.1<0,1,0>UB') -/* U */ -define(`CB', `g1.0<0,1,0>UB') -define(`CBCR', `g1.0<0,1,0>UW') - -define(`Y_BTI', `1') -define(`CB_BTI', `2') -define(`CBCR_BTI', `2') -define(`CR_BTI', `3') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* Y */ -shl(2) g16.0<1>UD ORIG 4:w {align1}; -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(4) g17.0<1>UB Y {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* UV */ -shl(1) g16.0<1>UD ORIGX 4:w {align1}; -shl(1) g16.4<1>UD ORIGY 3:w {align1}; - -/* 16x8 block */ -mov(1) g16.8<1>UD 0x0007000fUD {align1}; - -mov(2) g17.0<1>UW CBCR {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(CBCR_BTI, 0, 10, 12) mlen 5 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b b/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b deleted file mode 100644 index 0c4c5cea..00000000 --- a/src/shaders/post_processing/gen8/clear_pl3_8bit.g8b +++ /dev/null @@ -1,20 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00200009, 0x22001208, 0x1e450004, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00400001, 0x22202288, 0x00000022, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00030003 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00030003 }, - { 0x00000001, 0x22080608, 0x00000000, 0x00070007 }, - { 0x00400001, 0x22202288, 0x00000020, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8002 }, - { 0x00400001, 0x22202288, 0x00000021, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x060a8003 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa b/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa deleted file mode 100644 index 67662681..00000000 --- a/src/shaders/post_processing/gen8/clear_pl3_8bit.gxa +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Y */ -define(`Y', `g1.2<0,1,0>UB') -/* V */ -define(`CR', `g1.1<0,1,0>UB') -/* U */ -define(`CB', `g1.0<0,1,0>UB') -define(`CBCR', `g1.0<0,1,0>UW') - -define(`Y_BTI', `1') -define(`CB_BTI', `2') -define(`CBCR_BTI', `2') -define(`CR_BTI', `3') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* Y */ -shl(2) g16.0<1>UD ORIG 4:w {align1}; -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(4) g17.0<1>UB Y {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* U */ -shl(1) g16.0<1>UD ORIGX 3:w {align1}; -shl(1) g16.4<1>UD ORIGY 3:w {align1}; - -/* 8x8 block */ -mov(1) g16.8<1>UD 0x00070007UD {align1}; - -mov(4) g17.0<1>UB CB {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; - -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(CB_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; - -/* V */ -mov(4) g17.0<1>UB CR {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; - -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(CR_BTI, 0, 10, 12) mlen 3 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/src/shaders/post_processing/gen8/clear_rgbx.g8b b/src/shaders/post_processing/gen8/clear_rgbx.g8b deleted file mode 100644 index e88addb7..00000000 --- a/src/shaders/post_processing/gen8/clear_rgbx.g8b +++ /dev/null @@ -1,21 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00060006 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00000001, 0x22232288, 0x00000023, 0x00000000 }, - { 0x00000001, 0x22222288, 0x00000020, 0x00000000 }, - { 0x00000001, 0x22212288, 0x00000021, 0x00000000 }, - { 0x00000001, 0x22202288, 0x00000022, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_rgbx.gxa b/src/shaders/post_processing/gen8/clear_rgbx.gxa deleted file mode 100644 index 5ca6ea75..00000000 --- a/src/shaders/post_processing/gen8/clear_rgbx.gxa +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Red */ -define(`R', `g1.2<0,1,0>UB') -/* Green */ -define(`G', `g1.1<0,1,0>UB') -/* Blue */ -define(`B', `g1.0<0,1,0>UB') - -define(`RGBX_BTI', `1') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* RGBA/RGBX */ -shl(1) g16.0<1>UD ORIGX 6:w {align1}; -shl(1) g16.4<1>UD ORIGY 4:w {align1}; - -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(1) g17.3<1>UB ALPHA {align1}; -mov(1) g17.2<1>UB B {align1}; -mov(1) g17.1<1>UB G {align1}; -mov(1) g17.0<1>UB R {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(RGBX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/src/shaders/post_processing/gen8/clear_uyvy.g8b b/src/shaders/post_processing/gen8/clear_uyvy.g8b deleted file mode 100644 index b6675acb..00000000 --- a/src/shaders/post_processing/gen8/clear_uyvy.g8b +++ /dev/null @@ -1,16 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00200001, 0x42212288, 0x00000022, 0x00000000 }, - { 0x00000001, 0x22202288, 0x00000020, 0x00000000 }, - { 0x00000001, 0x22222288, 0x00000021, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_uyvy.gxa b/src/shaders/post_processing/gen8/clear_uyvy.gxa deleted file mode 100644 index 8dffacc9..00000000 --- a/src/shaders/post_processing/gen8/clear_uyvy.gxa +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Y */ -define(`Y', `g1.2<0,1,0>UB') -/* V */ -define(`CR', `g1.1<0,1,0>UB') -/* U */ -define(`CB', `g1.0<0,1,0>UB') -define(`CBCR', `g1.0<0,1,0>UW') - -define(`Y_BTI', `1') -define(`CB_BTI', `2') -define(`CBCR_BTI', `2') -define(`CR_BTI', `3') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* Y */ -shl(1) g16.0<1>UD ORIGX 5:w {align1}; -shl(1) g16.4<1>UD ORIGY 4:w {align1}; - -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(2) g17.1<2>UB Y {align1}; -mov(1) g17.0<1>UB CB {align1}; -mov(1) g17.2<1>UB CR {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/src/shaders/post_processing/gen8/clear_yuy2.g8b b/src/shaders/post_processing/gen8/clear_yuy2.g8b deleted file mode 100644 index 493d7abf..00000000 --- a/src/shaders/post_processing/gen8/clear_yuy2.g8b +++ /dev/null @@ -1,16 +0,0 @@ - { 0x00600001, 0x22000208, 0x008d0000, 0x00000000 }, - { 0x00000009, 0x22001208, 0x1e000004, 0x00050005 }, - { 0x00000009, 0x22041208, 0x1e000006, 0x00040004 }, - { 0x00000001, 0x22080608, 0x00000000, 0x000f000f }, - { 0x00200001, 0x42202288, 0x00000022, 0x00000000 }, - { 0x00000001, 0x22212288, 0x00000020, 0x00000000 }, - { 0x00000001, 0x22232288, 0x00000021, 0x00000000 }, - { 0x00800001, 0x22200208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22600208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22a00208, 0x00000220, 0x00000000 }, - { 0x00800001, 0x22e00208, 0x00000220, 0x00000000 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00000040, 0x22000208, 0x1e000200, 0x00100010 }, - { 0x0c800031, 0x24000a40, 0x0e000200, 0x120a8001 }, - { 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 }, - { 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 }, diff --git a/src/shaders/post_processing/gen8/clear_yuy2.gxa b/src/shaders/post_processing/gen8/clear_yuy2.gxa deleted file mode 100644 index d6840a9a..00000000 --- a/src/shaders/post_processing/gen8/clear_yuy2.gxa +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright © 2018 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: - * Xiang Haihao <haihao.xiang@intel.com> - * - */ - -/* - * Registers - * g0 header - * g1-g3 static parameters (constant) - * g16-g24 payload for write message - */ -define(`ORIG', `g0.4<2,2,1>UW') -define(`ORIGX', `g0.4<0,1,0>UW') -define(`ORIGY', `g0.6<0,1,0>UW') - -define(`ALPHA', `g1.3<0,1,0>UB') -/* Y */ -define(`Y', `g1.2<0,1,0>UB') -/* V */ -define(`CR', `g1.1<0,1,0>UB') -/* U */ -define(`CB', `g1.0<0,1,0>UB') -define(`CBCR', `g1.0<0,1,0>UW') - -define(`Y_BTI', `1') -define(`CB_BTI', `2') -define(`CBCR_BTI', `2') -define(`CR_BTI', `3') - -/* Thread header */ -mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1}; - -/* Y */ -shl(1) g16.0<1>UD ORIGX 5:w {align1}; -shl(1) g16.4<1>UD ORIGY 4:w {align1}; - -/* 16x16 block */ -mov(1) g16.8<1>UD 0x000f000fUD {align1}; - -mov(2) g17.0<2>UB Y {align1}; -mov(1) g17.1<1>UB CB {align1}; -mov(1) g17.3<1>UB CR {align1}; -mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr}; -mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr}; -/* - * write(p0, p1, p2, p3) - * p0: binding table index - * p1: message control, default is 0, - * p2: message type, 10 is media_block_write - * p3: cache type, 12 is data cache data port 1 - */ -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1}; -send(16) 16 acc0<1>UW null write(Y_BTI, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; |