diff options
author | Decai Lin <decai.lin@intel.com> | 2019-03-05 14:50:59 +0800 |
---|---|---|
committer | XinfengZhang <carl.zhang@intel.com> | 2019-03-04 22:59:05 -0800 |
commit | 16d32656d62132cb54969340d375c5e3ca51bd4f (patch) | |
tree | c567526469dea6d801cda226da7549b67c731e39 /va | |
parent | b3694671c7847bdf9830e8c64171aff4c97180e4 (diff) | |
download | libva-16d32656d62132cb54969340d375c5e3ca51bd4f.tar.gz |
va/va_trace: add trace support for RIR(rolling intra refresh).
Signed-off-by: Decai Lin <decai.lin@intel.com>
Diffstat (limited to 'va')
-rwxr-xr-x | va/va_trace.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/va/va_trace.c b/va/va_trace.c index 31af56f..0a17e5c 100755 --- a/va/va_trace.c +++ b/va/va_trace.c @@ -3287,6 +3287,18 @@ static void va_TraceVAEncMiscParameterBuffer( } break; } + case VAEncMiscParameterTypeRIR: + { + VAEncMiscParameterRIR *p = (VAEncMiscParameterRIR *)tmp->data; + + va_TraceMsg(trace_ctx, "\t--VAEncMiscParameterRIR\n"); + va_TraceMsg(trace_ctx, "\trir_flags.bits.enable_rir_column = %d\n", p->rir_flags.bits.enable_rir_column); + va_TraceMsg(trace_ctx, "\trir_flags.bits.enable_rir_row = %d\n", p->rir_flags.bits.enable_rir_row); + va_TraceMsg(trace_ctx, "\tintra_insertion_location = %d\n", p->intra_insertion_location); + va_TraceMsg(trace_ctx, "\tintra_insert_size = %d\n", p->intra_insert_size); + va_TraceMsg(trace_ctx, "\tqp_delta_for_inserted_intra = %d\n", p->qp_delta_for_inserted_intra); + break; + } default: va_TraceMsg(trace_ctx, "Unknown VAEncMiscParameterBuffer(type = %d):\n", tmp->type); va_TraceVABuffers(dpy, context, buffer, type, size, num_elements, data); |