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-rw-r--r--i965_drv_video/i965_defines.h3
-rw-r--r--i965_drv_video/i965_media.c14
2 files changed, 17 insertions, 0 deletions
diff --git a/i965_drv_video/i965_defines.h b/i965_drv_video/i965_defines.h
index e50b41b..aa2baa3 100644
--- a/i965_drv_video/i965_defines.h
+++ b/i965_drv_video/i965_defines.h
@@ -35,6 +35,9 @@
#define CMD_CONSTANT_COLOR CMD(3, 1, 1)
#define CMD_3DPRIMITIVE CMD(3, 3, 0)
+#define CMD_DEPTH_BUFFER CMD(3, 1, 5)
+#define I965_DEPTHFORMAT_D32_FLOAT 1
+
#define BASE_ADDRESS_MODIFY (1 << 0)
#define PIPELINE_SELECT_3D 0
diff --git a/i965_drv_video/i965_media.c b/i965_drv_video/i965_media.c
index 6a2971c..929e04f 100644
--- a/i965_drv_video/i965_media.c
+++ b/i965_drv_video/i965_media.c
@@ -166,6 +166,19 @@ i965_media_constant_buffer(VADriverContextP ctx, struct decode_state *decode_sta
ADVANCE_BATCH(ctx);
}
+static void
+i965_media_depth_buffer(VADriverContextP ctx)
+{
+ BEGIN_BATCH(ctx, 6);
+ OUT_BATCH(ctx, CMD_DEPTH_BUFFER | 4);
+ OUT_BATCH(ctx, (I965_DEPTHFORMAT_D32_FLOAT << 18) |
+ (I965_SURFACE_NULL << 29));
+ OUT_BATCH(ctx, 0);
+ OUT_BATCH(ctx, 0);
+ OUT_BATCH(ctx, 0);
+ ADVANCE_BATCH();
+}
+
static void
i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_state)
{
@@ -174,6 +187,7 @@ i965_media_pipeline_setup(VADriverContextP ctx, struct decode_state *decode_stat
intel_batchbuffer_start_atomic(ctx, 0x1000);
intel_batchbuffer_emit_mi_flush(ctx); /* step 1 */
+ i965_media_depth_buffer(ctx);
i965_media_pipeline_select(ctx); /* step 2 */
i965_media_urb_layout(ctx); /* step 3 */
i965_media_pipeline_state(ctx); /* step 4 */