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| author | Thierry Reding <treding@nvidia.com> | 2015-01-28 16:32:52 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-02 18:49:23 +0200 |
| commit | 5c1c071a3667600d1b8426dba031b2d4a20a3efa (patch) | |
| tree | 144ef5ced455205b60db36fb46660739ffb82d84 | |
| parent | 375e118437716acdccda224abb3d464ecfe92884 (diff) | |
| download | linux-next-5c1c071a3667600d1b8426dba031b2d4a20a3efa.tar.gz | |
drm/tegra: hdmi: Name register fields consistently
Name the fields of the SOR_SEQ_CTL register consistently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 05213b2ec2bd..06ab1783bba1 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -952,7 +952,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, } tegra_hdmi_writel(hdmi, - SOR_SEQ_CTL_PU_PC(0) | + SOR_SEQ_PU_PC(0) | SOR_SEQ_PU_PC_ALT(0) | SOR_SEQ_PD_PC(8) | SOR_SEQ_PD_PC_ALT(8), diff --git a/drivers/gpu/drm/tegra/hdmi.h b/drivers/gpu/drm/tegra/hdmi.h index 919a19df4e1b..a882514389cd 100644 --- a/drivers/gpu/drm/tegra/hdmi.h +++ b/drivers/gpu/drm/tegra/hdmi.h @@ -201,7 +201,7 @@ #define HDMI_NV_PDISP_SOR_CRCB 0x5d #define HDMI_NV_PDISP_SOR_BLANK 0x5e #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f -#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0) +#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0) #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4) #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8) #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12) |