diff options
author | Tony Lindgren <tony@atomide.com> | 2020-11-16 12:57:13 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2020-11-16 13:11:17 +0200 |
commit | ffbf46a3624cad94ee087a5d486b423e43f6bc1f (patch) | |
tree | fd003d4e5713c6eb71d980f05cbce14576a15ebe /arch/arm/boot/dts/am4372.dtsi | |
parent | 04af40fc7433555d31d73b698f0fb292b0bf9d7c (diff) | |
download | linux-next-ffbf46a3624cad94ee087a5d486b423e43f6bc1f.tar.gz |
ARM: OMAP2+: Drop legacy platform data for am4 ocmcram
We can now probe devices with ti-sysc interconnect driver and dts
data. Let's drop the related platform data and custom ti,hwmods
dts property.
Note that we need to use "ti,no-idle" here.
Cc: Dave Gerlach <d-gerlach@ti.com>
Cc: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am4372.dtsi')
-rw-r--r-- | arch/arm/boot/dts/am4372.dtsi | 36 |
1 files changed, 23 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 204556144ce7..ab70722e866f 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -503,23 +503,33 @@ }; }; - ocmcram: sram@40300000 { - compatible = "mmio-sram"; - reg = <0x40300000 0x40000>; /* 256k */ - ranges = <0x0 0x40300000 0x40000>; + target-module@40300000 { + compatible = "ti,sysc-omap4-simple", "ti,sysc"; + clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; + clock-names = "fck"; + ti,no-idle; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40300000 0x40000>; - pm_sram_code: pm-code-sram@0 { - compatible = "ti,sram"; - reg = <0x0 0x1000>; - protect-exec; - }; + ocmcram: sram@0 { + compatible = "mmio-sram"; + reg = <0 0x40000>; /* 256k */ + ranges = <0 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; - pm_sram_data: pm-data-sram@1000 { - compatible = "ti,sram"; - reg = <0x1000 0x1000>; - pool; + pm_sram_code: pm-code-sram@0 { + compatible = "ti,sram"; + reg = <0x0 0x1000>; + protect-exec; + }; + + pm_sram_data: pm-data-sram@1000 { + compatible = "ti,sram"; + reg = <0x1000 0x1000>; + pool; + }; }; }; |