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| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2018-05-10 08:48:23 +1000 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2018-05-10 08:48:23 +1000 |
| commit | 6b81371826fa536ef4e08687d37b54fa9bce6966 (patch) | |
| tree | 1ecbcfc1ff8af0b345ca9cff3959e14b4ac8e26a /arch/arm/boot/dts/imx7s.dtsi | |
| parent | cc77775bd92d656fc9124a593382e4fa6bd117de (diff) | |
| parent | 75ed360763f2dc5776a372c3303d1bae501769ad (diff) | |
| download | linux-next-6b81371826fa536ef4e08687d37b54fa9bce6966.tar.gz | |
Merge remote-tracking branch 'imx-mxs/for-next'
Diffstat (limited to 'arch/arm/boot/dts/imx7s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 4d42335c0dee..b416d2b69713 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -173,6 +173,17 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon =<&anatop>; + nvmem-cells = <&tempmon_calib>, + <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + }; + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&intc>; @@ -540,16 +551,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon =<&anatop>; - nvmem-cells = <&tempmon_calib>, - <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - anatop: anatop@30360000 { compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; @@ -573,6 +574,21 @@ anatop-max-voltage = <1200000>; anatop-enable-bit = <0>; }; + + reg_1p2: regulator-vdd1p2@30360220 { + reg = <0x30360220>; + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; + }; }; snvs: snvs@30370000 { @@ -868,6 +884,7 @@ crypto: caam@30900000 { compatible = "fsl,sec-v4.0"; + fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; reg = <0x30900000 0x40000>; |