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authorKavyasree Kotagiri <kavyasree.kotagiri@microchip.com>2022-02-21 13:38:58 +0530
committerNicolas Ferre <nicolas.ferre@microchip.com>2022-02-24 15:44:03 +0100
commit290deaa10c50932089a459dc91f8d496c72d85e7 (patch)
treeec87758a046e28f0a9bd5ef2d562083804e8025e /arch/arm/boot/dts/lan966x-pcb8291.dts
parente783362eb54cd99b2cac8b3a9aeac942e6f6ac07 (diff)
downloadlinux-next-290deaa10c50932089a459dc91f8d496c72d85e7.tar.gz
ARM: dts: add DT for lan966 SoC and 2-port board pcb8291
This patch adds basic DT for Microchip lan966x SoC and associated board pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs. Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG and MCAN0. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Reviewed-by: Michael Walle <michael@walle.cc> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220221080858.14233-1-kavyasree.kotagiri@microchip.com
Diffstat (limited to 'arch/arm/boot/dts/lan966x-pcb8291.dts')
-rw-r--r--arch/arm/boot/dts/lan966x-pcb8291.dts64
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
new file mode 100644
index 000000000000..3281af90ac6d
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x_pcb8291.dts - Device Tree file for PCB8291
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+ model = "Microchip EVB - LAN9662";
+ compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &usart3;
+ };
+};
+
+&gpio {
+ fc_shrd7_pins: fc_shrd7-pins {
+ pins = "GPIO_49";
+ function = "fc_shrd7";
+ };
+
+ fc_shrd8_pins: fc_shrd8-pins {
+ pins = "GPIO_54";
+ function = "fc_shrd8";
+ };
+
+ fc3_b_pins: fcb3-spi-pins {
+ /* SCK, RXD, TXD */
+ pins = "GPIO_51", "GPIO_52", "GPIO_53";
+ function = "fc3_b";
+ };
+
+ can0_b_pins: can0_b_pins {
+ /* RX, TX */
+ pins = "GPIO_35", "GPIO_36";
+ function = "can0_b";
+ };
+};
+
+&can0 {
+ pinctrl-0 = <&can0_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&flx3 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+ status = "okay";
+
+ usart3: serial@200 {
+ pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+};
+
+&watchdog {
+ status = "okay";
+};