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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2019-11-17 14:59:23 +0100
committerJerome Brunet <jbrunet@baylibre.com>2019-12-11 14:06:28 +0100
commit25d316989e2b1beebaa69e6c3e76e762776c93de (patch)
tree637d3f08dd1b249fcbde941095535df78cc8e50f /arch/arm/boot/dts/meson8b-odroidc1.dts
parent51b6fe7e66eee0fe353ff8157c64d16b971fac39 (diff)
downloadlinux-next-25d316989e2b1beebaa69e6c3e76e762776c93de.tar.gz
dt-bindings: clock: meson8b: add the clock inputs
The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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