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author | Kunihiko Hayashi <hayashi.kunihiko@socionext.com> | 2022-11-18 01:32:19 +0900 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2022-11-21 10:56:10 +0100 |
commit | bdeaf22dfacaea87003abe7498f91b4e516861bf (patch) | |
tree | 9ba96d06fb221f47f6893cd10f7f14c40f2c2a34 /arch/arm/boot/dts/uniphier-pro5-epcore.dts | |
parent | 2dbcd8b4f208de94c43c76ef401a87e64457ee2c (diff) | |
download | linux-next-bdeaf22dfacaea87003abe7498f91b4e516861bf.tar.gz |
ARM: dts: uniphier: Add Pro5 board support
Initial version of devicetree sources for Pro5 EPCORE and ProEX boards.
These boards have UART, I2C, USB, eMMC and PCI endpoint in common.
Pro5 EPCORE board is a kind of Pro5 reference board with PCIe endpoint
card edge connector.
ProEX board shares peripherals with Linux and other systems, and some
of these ports are available in Linux.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/20221117163219.3673-3-hayashi.kunihiko@socionext.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-pro5-epcore.dts')
-rw-r--r-- | arch/arm/boot/dts/uniphier-pro5-epcore.dts | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/uniphier-pro5-epcore.dts new file mode 100644 index 000000000000..ed759dcc3216 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro5-epcore.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE) + * + * Copyright (C) 2021 Socionext Inc. + * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + */ + +/dts-v1/; +#include "uniphier-pro5.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro5 EP-CORE Board"; + compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +ðsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&pcie_ep { + status = "okay"; +}; |