diff options
| author | Varalaxmi Bingi <varalaxmi.bingi@amd.com> | 2023-05-02 15:53:35 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-05-12 13:25:09 +0200 |
| commit | a9d37bd427ba0c873ebeef6fbd74410669cb2c54 (patch) | |
| tree | 4cc9505757716a8c13c14ee39a867280bf509025 /arch/arm/boot/dts | |
| parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
| download | linux-next-a9d37bd427ba0c873ebeef6fbd74410669cb2c54.tar.gz | |
ARM: zynq: dts: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for Zynq to maximum rate of 400kHz.
Current default value is 100kHz.
Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4dde5d1eb8e4572dae4295a19a4c83002a58e5da.1683035611.git.michal.simek@amd.com
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index cd9931f6bcbd..a7db3f3009f2 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -149,6 +149,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -160,6 +161,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; |