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authorAndrew Davis <afd@ti.com>2022-10-28 09:24:15 -0500
committerNishanth Menon <nm@ti.com>2022-11-03 21:46:01 -0500
commit7ff8432c272e3556461b7c9daad8156ae446e812 (patch)
tree802a38804383b4b8af34439db229c42b40ade030 /arch/arm64/boot/dts/ti/k3-am654-base-board.dts
parentb08bf4a5c0ed0a6b8472ca78ccf416d73d2609aa (diff)
downloadlinux-next-7ff8432c272e3556461b7c9daad8156ae446e812.tar.gz
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am654-base-board.dts')
-rw-r--r--arch/arm64/boot/dts/ti/k3-am654-base-board.dts16
1 files changed, 0 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index bf6a6fe3d7ba..a61060c6bc19 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -415,22 +415,6 @@
status = "disabled";
};
-&pcie0_rc {
- status = "disabled";
-};
-
-&pcie0_ep {
- status = "disabled";
-};
-
-&pcie1_rc {
- status = "disabled";
-};
-
-&pcie1_ep {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
interrupts = <436>;