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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-03-31 08:51:45 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-03-31 08:51:45 -0700 |
commit | d71e064449a704a026fa032ec852d532f08aefa1 (patch) | |
tree | f282611ec43985fdbf988eede52a88e0465e78fc /arch/mips/sgi-ip32/ip32-irq.c | |
parent | 58233ccf94607c1df2c545b689c52c0b002f054e (diff) | |
parent | ba15533275dd70238b523417d222d43fb40dac9d (diff) | |
download | linux-next-d71e064449a704a026fa032ec852d532f08aefa1.tar.gz |
Merge tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- loongson64 irq rework
- dmi support loongson
- replace setup_irq() by request_irq()
- jazz cleanups
- minor cleanups and fixes
* tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (44 commits)
MIPS: ralink: mt7621: Fix soc_device introduction
MIPS: Exclude more dsemul code when CONFIG_MIPS_FP_SUPPORT=n
MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3
MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC
MAINTAINERS: Update Loongson64 entry
MIPS: Loongson64: Load built-in dtbs
MIPS: Loongson64: Add generic dts
dt-bindings: mips: Add loongson boards
MIPS: Loongson64: Drop legacy IRQ code
dt-bindings: interrupt-controller: Add Loongson-3 HTPIC
irqchip: Add driver for Loongson-3 HyperTransport PIC controller
dt-bindings: interrupt-controller: Add Loongson LIOINTC
irqchip: loongson-liointc: Workaround LPC IRQ Errata
irqchip: Add driver for Loongson I/O Local Interrupt Controller
docs: mips: remove no longer needed au1xxx_ide.rst documentation
MIPS: Alchemy: remove no longer used au1xxx_ide.h header
ide: remove no longer used au1xxx-ide driver
MIPS: Add support for Desktop Management Interface (DMI)
firmware: dmi: Add macro SMBIOS_ENTRY_POINT_SCAN_START
MIPS: ralink: mt7621: introduce 'soc_device' initialization
...
Diffstat (limited to 'arch/mips/sgi-ip32/ip32-irq.c')
-rw-r--r-- | arch/mips/sgi-ip32/ip32-irq.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index a6a0ff7f5aed..1bbd5bfb5458 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -111,16 +111,6 @@ static inline void flush_mace_bus(void) extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); -static struct irqaction memerr_irq = { - .handler = crime_memerr_intr, - .name = "CRIME memory error", -}; - -static struct irqaction cpuerr_irq = { - .handler = crime_cpuerr_intr, - .name = "CRIME CPU error", -}; - /* * This is for pure CRIME interrupts - ie not MACE. The advantage? * We get to split the register in half and do faster lookups. @@ -497,8 +487,12 @@ void __init arch_init_irq(void) break; } } - setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); - setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); + if (request_irq(CRIME_MEMERR_IRQ, crime_memerr_intr, 0, + "CRIME memory error", NULL)) + pr_err("Failed to register CRIME memory error interrupt\n"); + if (request_irq(CRIME_CPUERR_IRQ, crime_cpuerr_intr, 0, + "CRIME CPU error", NULL)) + pr_err("Failed to register CRIME CPU error interrupt\n"); #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) change_c0_status(ST0_IM, ALLINTS); |