diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2010-03-03 21:21:13 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2010-03-03 21:21:13 -0700 |
| commit | b9cc98697d1ca35a86bbb708acc6d93993c28f0f (patch) | |
| tree | 22bace58c86068483209b8b2d9a2b6238eb0c179 /drivers/dma/ioat/registers.h | |
| parent | aa75db0080603bae27961c0502812dfd0f522bb3 (diff) | |
| download | linux-next-b9cc98697d1ca35a86bbb708acc6d93993c28f0f.tar.gz | |
ioat3: interrupt coalescing
The hardware automatically disables further interrupts after each event
until rearmed. This allows a delay to be injected between the occurence
of the interrupt and the running of the cleanup routine. The delay is
scaled by the descriptor backlog and then written to the INTRDELAY
register which specifies the number of microseconds to hold off
interrupt delivery after an interrupt event occurs. According to
powertop this reduces the interrupt rate from ~5000 intr/s to ~150
intr/s per without affecting throughput (simple dd to a raid6 array).
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/dma/ioat/registers.h')
| -rw-r--r-- | drivers/dma/ioat/registers.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h index e8ae63baf588..1391798542b6 100644 --- a/drivers/dma/ioat/registers.h +++ b/drivers/dma/ioat/registers.h @@ -60,7 +60,7 @@ #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ -#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */ +#define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ |