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authorEvan Quan <evan.quan@amd.com>2023-04-07 17:12:15 +0800
committerAlex Deucher <alexander.deucher@amd.com>2023-04-13 00:14:44 -0400
commit6fe2ecdba34445a17049cda73a399d9685189efc (patch)
tree474a327c42b16c7bfa32d7956d8dff8fc4ae0db0 /drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
parentfd784a418ed832fbadfa846cef61741fdab0377a (diff)
downloadlinux-next-6fe2ecdba34445a17049cda73a399d9685189efc.tar.gz
drm/amd/pm: correct the pcie link state check for SMU13
Update the driver implementations to fit those data exposed by PMFW. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 0ef37837b164..7944ce80e5c3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -62,6 +62,12 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
+static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
+static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
+
+#define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx])
+#define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx])
+
struct smu_13_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;