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authorDaniel Vetter <daniel.vetter@ffwll.ch>2012-12-01 13:53:43 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-12-06 13:14:36 +0100
commit61168c53f5be309332006dbd967aaac501cde8b2 (patch)
tree3bba31f310912c523ef8b109f74828587780e67c /drivers/gpu/drm/drm_fb_cma_helper.c
parent52d7ecedac3f96fb562cb482c139015372728638 (diff)
downloadlinux-next-61168c53f5be309332006dbd967aaac501cde8b2.tar.gz
drm/i915: extract gmbus_wait_hw_status
The gmbus interrupt generation is rather fiddly: We can only ever enable one interrupt source (but we always want to check for NAK in addition to the real bit). And the bits in the gmbus status register don't map at all to the bis in the irq register. To prepare for this mess, start by extracting the hw status wait loop into it's own function, consolidate the NAK error handling a bit. To keep things flexible, pass in the status bit we care about (in addition to any NAK signalling). v2: I've failed to notice that the sense of GMBUS_ACTIVE is inverted, Chris Wilson gladly pointed that out for me. To keep things simple, ignore that case for now (we only need to idle the gmbus controller at the end of an entire i2c transaction, not after every message). Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/drm_fb_cma_helper.c')
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