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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2015-03-10 15:03:43 +0100 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2015-03-31 12:03:54 +0200 |
| commit | f7089d923eacb9c8e57d8492699662756881b54d (patch) | |
| tree | 9751d3e0c1daed286261d150b961e9b81be99bd1 /drivers/gpu/ipu-v3 | |
| parent | 91fd89660ba2e8ee59a587294fa9b17761691b05 (diff) | |
| download | linux-next-f7089d923eacb9c8e57d8492699662756881b54d.tar.gz | |
gpu: ipu-v3: limit pixel clock divider to 8-bits
The DI pixel clock divider bit field is only 8 bits wide for the
integer part, so limit the divider to the 1...255 interval before
deciding whether the internal clock can be used and before writing
to the register.
Reported-by: Felix Mellmann <felix.mellmann@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/ipu-v3')
| -rw-r--r-- | drivers/gpu/ipu-v3/ipu-di.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c index 3ddfb3d0b64d..2970c6bb668c 100644 --- a/drivers/gpu/ipu-v3/ipu-di.c +++ b/drivers/gpu/ipu-v3/ipu-di.c @@ -441,8 +441,7 @@ static void ipu_di_config_clock(struct ipu_di *di, in_rate = clk_get_rate(clk); div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); - if (div == 0) - div = 1; + div = clamp(div, 1U, 255U); clkgen0 = div << 4; } @@ -459,8 +458,7 @@ static void ipu_di_config_clock(struct ipu_di *di, clkrate = clk_get_rate(di->clk_ipu); div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); - if (div == 0) - div = 1; + div = clamp(div, 1U, 255U); rate = clkrate / div; error = rate / (sig->mode.pixelclock / 1000); @@ -483,8 +481,7 @@ static void ipu_di_config_clock(struct ipu_di *di, in_rate = clk_get_rate(clk); div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); - if (div == 0) - div = 1; + div = clamp(div, 1U, 255U); clkgen0 = div << 4; } |