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| author | Jason Gunthorpe <jgg@nvidia.com> | 2020-11-23 16:50:59 -0400 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2020-11-23 16:50:59 -0400 |
| commit | ed92f6a52b84c0c03ae9d829cf118c6e38e456fb (patch) | |
| tree | 7b85d805aa96e8b89e8be80bd03c6e43b1e6db62 /drivers/net/dsa/mv88e6xxx/global1.c | |
| parent | df0e4de29c75fab2d59b67b7542ea1e10d32c6e1 (diff) | |
| parent | 418baf2c28f3473039f2f7377760bd8f6897ae18 (diff) | |
| download | linux-next-ed92f6a52b84c0c03ae9d829cf118c6e38e456fb.tar.gz | |
Merge tag 'v5.10-rc5' into rdma.git for-next
For dependencies in following patches
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/net/dsa/mv88e6xxx/global1.c')
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx/global1.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c index f62aa83ca08d..33d443a37efc 100644 --- a/drivers/net/dsa/mv88e6xxx/global1.c +++ b/drivers/net/dsa/mv88e6xxx/global1.c @@ -75,6 +75,37 @@ static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); } +void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip) +{ + const unsigned long timeout = jiffies + 1 * HZ; + u16 val; + int err; + + /* Wait up to 1 second for the switch to finish reading the + * EEPROM. + */ + while (time_before(jiffies, timeout)) { + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); + if (err) { + dev_err(chip->dev, "Error reading status"); + return; + } + + /* If the switch is still resetting, it may not + * respond on the bus, and so MDIO read returns + * 0xffff. Differentiate between that, and waiting for + * the EEPROM to be done by bit 0 being set. + */ + if (val != 0xffff && + val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE)) + return; + + usleep_range(1000, 2000); + } + + dev_err(chip->dev, "Timeout waiting for EEPROM done"); +} + /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 |