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authorMarc St-Jean <stjeanma@pmc-sierra.com>2007-06-14 15:55:31 -0600
committerRalf Baechle <ralf@linux-mips.org>2007-07-10 17:33:03 +0100
commit9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa (patch)
tree91fa5a1a4605cdf0a1f1db21e22073b87735ce7a /include/asm-mips/mipsregs.h
parent35832e26f95ba14a6b6f0519441c5cb64cca6bf9 (diff)
downloadlinux-next-9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa.tar.gz
[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mipsregs.h')
-rw-r--r--include/asm-mips/mipsregs.h33
1 files changed, 33 insertions, 0 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 668db02c2804..706b3691f57e 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -15,6 +15,7 @@
#include <linux/linkage.h>
#include <asm/hazards.h>
+#include <asm/war.h>
/*
* The following macros are especially useful for __asm__
@@ -537,6 +538,9 @@
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
+#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+
+
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
@@ -1298,10 +1302,39 @@ static inline void tlb_probe(void)
static inline void tlb_read(void)
{
+#if MIPS34K_MISSED_ITLB_WAR
+ int res = 0;
+
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41610001 # dvpe $1 \n"
+ " move %0, $1 \n"
+ " ehb \n"
+ " .set pop \n"
+ : "=r" (res));
+
+ instruction_hazard();
+#endif
+
__asm__ __volatile__(
".set noreorder\n\t"
"tlbr\n\t"
".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+ if ((res & _ULCAST_(1)))
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41600021 # evpe \n"
+ " ehb \n"
+ " .set pop \n");
+#endif
}
static inline void tlb_write_indexed(void)