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-rw-r--r--drivers/pci/pcie/portdrv.h20
-rw-r--r--drivers/pci/pcie/portdrv_core.c13
2 files changed, 9 insertions, 24 deletions
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index cc1f8435ee20..aaeb9d21cba5 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -11,24 +11,10 @@
#include <linux/compiler.h>
-#if !defined(PCI_CAP_ID_PME)
-#define PCI_CAP_ID_PME 1
-#endif
-
-#if !defined(PCI_CAP_ID_EXP)
-#define PCI_CAP_ID_EXP 0x10
-#endif
-
-#define PORT_TYPE_MASK 0xf
-#define PORT_TO_SLOT_MASK 0x100
-#define SLOT_HP_CAPABLE_MASK 0x40
-#define PCIE_CAPABILITIES_REG 0x2
-#define PCIE_SLOT_CAPABILITIES_REG 0x14
-#define PCIE_PORT_DEVICE_MAXSERVICES 4
-#define PCIE_PORT_MSI_VECTOR_MASK 0x1f
+#define PCIE_PORT_DEVICE_MAXSERVICES 4
/*
- * According to the PCI Express Base Specification 2.0, the indices of the MSI-X
- * table entires used by port services must not exceed 31
+ * According to the PCI Express Base Specification 2.0, the indices of
+ * the MSI-X table entires used by port services must not exceed 31
*/
#define PCIE_PORT_MAX_MSIX_ENTRIES 32
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 9318b96bb255..413262eb95b7 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -109,8 +109,8 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
* used to generate the interrupt message."
*/
pos = pci_pcie_cap(dev);
- pci_read_config_word(dev, pos + PCIE_CAPABILITIES_REG, &reg16);
- entry = (reg16 >> 9) & PCIE_PORT_MSI_VECTOR_MASK;
+ pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
+ entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
if (entry >= nr_entries)
goto Error;
@@ -230,12 +230,11 @@ static int get_port_device_capability(struct pci_dev *dev)
u32 reg32;
pos = pci_pcie_cap(dev);
- pci_read_config_word(dev, pos + PCIE_CAPABILITIES_REG, &reg16);
+ pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
/* Hot-Plug Capable */
- if (reg16 & PORT_TO_SLOT_MASK) {
- pci_read_config_dword(dev,
- pos + PCIE_SLOT_CAPABILITIES_REG, &reg32);
- if (reg32 & SLOT_HP_CAPABLE_MASK)
+ if (reg16 & PCI_EXP_FLAGS_SLOT) {
+ pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, &reg32);
+ if (reg32 & PCI_EXP_SLTCAP_HPC)
services |= PCIE_PORT_SERVICE_HP;
}
/* AER capable */