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path: root/drivers/gpu/drm/tidss/tidss_dispc.c
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Diffstat (limited to 'drivers/gpu/drm/tidss/tidss_dispc.c')
-rw-r--r--drivers/gpu/drm/tidss/tidss_dispc.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c
index dd3c6a606ae2..ad93acc9abd2 100644
--- a/drivers/gpu/drm/tidss/tidss_dispc.c
+++ b/drivers/gpu/drm/tidss/tidss_dispc.c
@@ -24,9 +24,9 @@
#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
-#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fb_dma_helper.h>
#include <drm/drm_framebuffer.h>
-#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_gem_dma_helper.h>
#include <drm/drm_panel.h>
#include "tidss_crtc.h"
@@ -1954,16 +1954,16 @@ int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
}
static
-dma_addr_t dispc_plane_state_paddr(const struct drm_plane_state *state)
+dma_addr_t dispc_plane_state_dma_addr(const struct drm_plane_state *state)
{
struct drm_framebuffer *fb = state->fb;
- struct drm_gem_cma_object *gem;
+ struct drm_gem_dma_object *gem;
u32 x = state->src_x >> 16;
u32 y = state->src_y >> 16;
- gem = drm_fb_cma_get_gem_obj(state->fb, 0);
+ gem = drm_fb_dma_get_gem_obj(state->fb, 0);
- return gem->paddr + fb->offsets[0] + x * fb->format->cpp[0] +
+ return gem->dma_addr + fb->offsets[0] + x * fb->format->cpp[0] +
y * fb->pitches[0];
}
@@ -1971,16 +1971,16 @@ static
dma_addr_t dispc_plane_state_p_uv_addr(const struct drm_plane_state *state)
{
struct drm_framebuffer *fb = state->fb;
- struct drm_gem_cma_object *gem;
+ struct drm_gem_dma_object *gem;
u32 x = state->src_x >> 16;
u32 y = state->src_y >> 16;
if (WARN_ON(state->fb->format->num_planes != 2))
return 0;
- gem = drm_fb_cma_get_gem_obj(fb, 1);
+ gem = drm_fb_dma_get_gem_obj(fb, 1);
- return gem->paddr + fb->offsets[1] +
+ return gem->dma_addr + fb->offsets[1] +
(x * fb->format->cpp[1] / fb->format->hsub) +
(y * fb->pitches[1] / fb->format->vsub);
}
@@ -1993,17 +1993,17 @@ int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
u32 fourcc = state->fb->format->format;
u16 cpp = state->fb->format->cpp[0];
u32 fb_width = state->fb->pitches[0] / cpp;
- dma_addr_t paddr = dispc_plane_state_paddr(state);
+ dma_addr_t dma_addr = dispc_plane_state_dma_addr(state);
struct dispc_scaling_params scale;
dispc_vid_calc_scaling(dispc, state, &scale, lite);
dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, paddr & 0xffffffff);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)paddr >> 32);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, paddr & 0xffffffff);
- dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)paddr >> 32);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
+ dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
(scale.in_w - 1) | ((scale.in_h - 1) << 16));