| Commit message (Expand) | Author | Age | Files | Lines |
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| * | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234 | Thomas Gleixner | 2019-06-19 | 1 | -12/+1 |
| * | riscv: move flush_icache_{all,mm} to cacheflush.c | Gary Guo | 2019-05-16 | 1 | -49/+0 |
| * | RISC-V: Access CSRs using CSR numbers | Anup Patel | 2019-05-16 | 1 | -1/+1 |
| * | RISC-V: Fix minor checkpatch issues. | Atish Patra | 2019-05-16 | 1 | -2/+2 |
| * | RISC-V: Add RISC-V specific arch_match_cpu_phys_id | Atish Patra | 2019-04-30 | 1 | -0/+6 |
| * | RISC-V: Fixmap support and MM cleanups | Palmer Dabbelt | 2019-03-04 | 1 | -1/+1 |
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| * | | RISC-V: Allow hartid-to-cpuid function to fail. | Atish Patra | 2019-03-04 | 1 | -1/+0 |
| * | | RISC-V: Move cpuid to hartid mapping to SMP. | Atish Patra | 2019-03-04 | 1 | -0/+9 |
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| * | riscv: don't stop itself in smp_send_stop | Andreas Schwab | 2019-01-07 | 1 | -7/+36 |
| * | RISC-V: Show IPI stats | Anup Patel | 2018-10-22 | 1 | -7/+32 |
| * | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra | 2018-10-22 | 1 | -9/+15 |
| * | RISC-V: Add logical CPU indexing for RISC-V | Atish Patra | 2018-10-22 | 1 | -0/+19 |
| * | RISC-V: simplify software interrupt / IPI code | Christoph Hellwig | 2018-08-13 | 1 | -4/+2 |
| * | RISC-V: Fixes for clean allmodconfig build | Palmer Dabbelt | 2017-12-01 | 1 | -0/+7 |
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| | * | RISC-V: Provide stub of setup_profiling_timer() | Olof Johansson | 2017-11-30 | 1 | -0/+7 |
| * | | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman | 2017-11-30 | 1 | -0/+48 |
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| * | RISC-V: Init and Halt Code | Palmer Dabbelt | 2017-09-26 | 1 | -0/+110 |
