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path: root/arch/riscv/kernel/traps.c
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* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner2019-06-051-9/+1
* riscv: Support BUG() in kernel moduleVincent Chen2019-05-161-1/+1
* riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen2019-05-161-3/+17
* RISC-V: Access CSRs using CSR numbersAnup Patel2019-05-161-3/+3
* riscv: remove duplicate macros from ptrace.hChristoph Hellwig2019-04-251-1/+1
* RISC-V: Don't increment sepc after breakpoint.Jim Wilson2018-08-131-1/+0
* Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2018-06-161-1/+1
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| * riscv: no __user for probe_kernel_address()Luc Van Oostenryck2018-06-071-1/+1
* | signal/riscv: Replace do_trap_siginfo with force_sig_faultEric W. Biederman2018-04-251-8/+2
* | signal/riscv: Use force_sig_fault where appropriateEric W. Biederman2018-04-251-8/+1
* | signal: Ensure every siginfo we send has all bits initializedEric W. Biederman2018-04-251-0/+1
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* RISC-V: Init and Halt CodePalmer Dabbelt2017-09-261-0/+180
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