summaryrefslogtreecommitdiff
path: root/drivers/clk/mediatek
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen2022-05-1814-131/+127
* clk: mediatek: update compatible string for MT7986 ethsysSam Shih2022-05-181-1/+1
* clk: mediatek: Add MT8186 ipesys clock supportChun-Jie Chen2022-04-252-1/+56
* clk: mediatek: Add MT8186 mdpsys clock supportChun-Jie Chen2022-04-252-1/+81
* clk: mediatek: Add MT8186 camsys clock supportChun-Jie Chen2022-04-252-1/+92
* clk: mediatek: Add MT8186 vencsys clock supportChun-Jie Chen2022-04-252-1/+52
* clk: mediatek: Add MT8186 vdecsys clock supportChun-Jie Chen2022-04-252-1/+89
* clk: mediatek: Add MT8186 imgsys clock supportChun-Jie Chen2022-04-252-1/+70
* clk: mediatek: Add MT8186 wpesys clock supportChun-Jie Chen2022-04-252-1/+52
* clk: mediatek: Add MT8186 mmsys clock supportChun-Jie Chen2022-04-252-1/+112
* clk: mediatek: Add MT8186 mfgsys clock supportChun-Jie Chen2022-04-252-1/+50
* clk: mediatek: Add MT8186 imp i2c wrapper clock supportChun-Jie Chen2022-04-252-1/+68
* clk: mediatek: Add MT8186 apmixedsys clock supportChun-Jie Chen2022-04-252-1/+135
* clk: mediatek: Add MT8186 infrastructure clock supportChun-Jie Chen2022-04-252-1/+217
* clk: mediatek: Add MT8186 topckgen clock supportChun-Jie Chen2022-04-252-1/+781
* clk: mediatek: Add MT8186 mcusys clock supportChun-Jie Chen2022-04-253-0/+117
* clk: mediatek: Warn if clk IDs are duplicatedChen-Yu Tsai2022-02-175-6/+34
* clk: mediatek: mt8195: Implement remove functionsChen-Yu Tsai2022-02-175-0/+83
* clk: mediatek: mt8195: Implement error handling in probe functionsChen-Yu Tsai2022-02-175-18/+61
* clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()Chen-Yu Tsai2022-02-1714-0/+14
* clk: mediatek: Unregister clks in mtk_clk_simple_probe() error pathChen-Yu Tsai2022-02-171-1/+3
* clk: mediatek: mtk: Implement error handling in register APIsChen-Yu Tsai2022-02-172-35/+103
* clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai2022-02-172-7/+22
* clk: mediatek: mux: Implement error handling in register APIChen-Yu Tsai2022-02-171-1/+14
* clk: mediatek: mux: Reverse check for existing clk to reduce nesting levelChen-Yu Tsai2022-02-171-7/+8
* clk: mediatek: gate: Implement error handling in register APIChen-Yu Tsai2022-02-171-1/+14
* clk: mediatek: cpumux: Implement error handling in register APIChen-Yu Tsai2022-02-171-1/+14
* clk: mediatek: mtk: Clean up included headersChen-Yu Tsai2022-02-172-13/+12
* clk: mediatek: Add mtk_clk_simple_remove()Chen-Yu Tsai2022-02-172-0/+16
* clk: mediatek: Implement mtk_clk_unregister_composites() APIChen-Yu Tsai2022-02-172-0/+48
* clk: mediatek: Implement mtk_clk_unregister_divider_clks() APIChen-Yu Tsai2022-02-172-3/+24
* clk: mediatek: Implement mtk_clk_unregister_factors() APIChen-Yu Tsai2022-02-172-2/+24
* clk: mediatek: Implement mtk_clk_unregister_fixed_clks() APIChen-Yu Tsai2022-02-172-2/+24
* clk: mediatek: pll: Clean up included headersChen-Yu Tsai2022-02-171-5/+7
* clk: mediatek: pll: Implement unregister APIChen-Yu Tsai2022-02-172-0/+57
* clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai2022-02-1719-57/+91
* clk: mediatek: mux: Clean up included headersChen-Yu Tsai2022-02-172-5/+14
* clk: mediatek: mux: Internalize struct mtk_clk_muxChen-Yu Tsai2022-02-172-8/+8
* clk: mediatek: mux: Implement unregister APIChen-Yu Tsai2022-02-172-0/+38
* clk: mediatek: cpumux: Clean up included headersChen-Yu Tsai2022-02-172-0/+7
* clk: mediatek: cpumux: Internalize struct mtk_clk_cpumuxChen-Yu Tsai2022-02-172-8/+8
* clk: mediatek: cpumux: Implement unregister APIChen-Yu Tsai2022-02-172-0/+34
* clk: mediatek: gate: Clean up included headersChen-Yu Tsai2022-02-172-11/+10
* clk: mediatek: gate: Implement unregister APIChen-Yu Tsai2022-02-172-0/+38
* clk: mediatek: gate: Internalize clk implementationChen-Yu Tsai2022-02-172-41/+25
* clk: mediatek: gate: Consolidate gate type clk related codeChen-Yu Tsai2022-02-174-77/+77
* clk: mediatek: Use %pe to print errorsChen-Yu Tsai2022-02-176-25/+13
* clk: mediatek: Fix memory leaks on probeJosé Expósito2022-01-241-6/+30
* clk: mediatek: relicense mt7986 clock driver to GPL-2.0Sam Shih2022-01-193-3/+3
* clk: mediatek: add mt7986 clock supportSam Shih2022-01-066-0/+819
View Lorry Controller Status