summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: r8a779f0: Add HSCIF clocksWolfram Sang2022-06-171-0/+4
* clk: renesas: r8a779f0: Add PCIe clocksYoshihiro Shimoda2022-06-171-0/+2
* clk: renesas: r8a779f0: Add Z0 and Z1 clock supportGeert Uytterhoeven2022-06-171-0/+2
* clk: renesas: rza1: Remove struct rz_cpgGeert Uytterhoeven2022-06-131-18/+15
* clk: renesas: r8a7779: Remove struct r8a7779_cpgGeert Uytterhoeven2022-06-131-18/+9
* clk: renesas: r8a7778: Remove struct r8a7778_cpgGeert Uytterhoeven2022-06-131-22/+9
* clk: renesas: sh73a0: Remove sh73a0_cpg.regGeert Uytterhoeven2022-06-131-13/+13
* clk: renesas: r8a7740: Remove r8a7740_cpg.regGeert Uytterhoeven2022-06-131-10/+10
* clk: renesas: r8a73a4: Remove r8a73a4_cpg.regGeert Uytterhoeven2022-06-131-11/+11
* clk: renesas: r8a779f0: Add SDHI0 clockWolfram Sang2022-06-131-0/+1
* clk: renesas: r8a779f0: Add thermal clockWolfram Sang2022-06-131-0/+1
* clk: renesas: rzg2l: Fix reset status functionBiju Das2022-06-071-1/+1
* clk: renesas: r9a06g032: Fix UART clkgrp bitselRalph Siemsen2022-06-061-4/+4
* clk: renesas: r9a06g032: Drop some unused fieldsRalph Siemsen2022-06-061-13/+11
* clk: renesas: r9a09g011: Add WDT clock and reset entriesPhil Edworthy2022-06-061-0/+3
* clk: renesas: r9a09g011: Add PFC clock and reset entriesPhil Edworthy2022-06-061-0/+2
* clk: renesas: r9a07g044: Add POEG clock and reset entriesBiju Das2022-06-061-1/+13
* clk: renesas: r9a07g044: Add GPT clock and reset entryBiju Das2022-06-061-1/+4
* Merge tag 'dmaengine-5.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds2022-05-291-1/+39
|\
| * clk: renesas: r9a06g032: Probe possible childrenMiquel Raynal2022-05-191-0/+5
| * clk: renesas: r9a06g032: Export function to set dmamuxMiquel Raynal2022-05-191-1/+34
* | clk: renesas: r9a09g011: Add eth clock and reset entriesPhil Edworthy2022-05-061-5/+9
* | clk: renesas: Add RZ/V2M support using the rzg2l driverPhil Edworthy2022-05-065-0/+181
* | clk: renesas: rzg2l: Add support for RZ/V2M reset monitor regPhil Edworthy2022-05-052-3/+17
* | clk: renesas: rzg2l: Make use of CLK_MON registers optionalPhil Edworthy2022-05-054-1/+16
* | clk: renesas: rzg2l: Set HIWORD mask for all mux and dividersPhil Edworthy2022-05-053-31/+19
* | clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-053-6/+12
* | clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-053-22/+19
* | clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven2022-05-051-1/+1
* | clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das2022-05-051-0/+6
* | clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das2022-05-051-0/+6
* | clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das2022-05-051-0/+9
* | clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Co...Biju Das2022-05-051-0/+18
* | clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das2022-05-051-1/+16
* | clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das2022-05-051-1/+8
* | clk: renesas: r9a07g044: Add M4 Clock supportBiju Das2022-05-051-1/+18
* | clk: renesas: r9a07g044: Add M3 Clock supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das2022-05-051-1/+4
* | clk: renesas: r9a07g044: Add M1 clock supportBiju Das2022-05-051-1/+10
* | clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2022-05-052-0/+136
* | clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2022-05-052-0/+103
* | clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2022-05-052-0/+235
* | clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda2022-04-295-0/+231
* | clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda2022-04-294-16/+24
* | clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das2022-04-281-0/+10
* | clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das2022-04-281-0/+9
* | clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das2022-04-281-0/+5
* | clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das2022-04-281-0/+12
* | clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das2022-04-281-0/+20
* | clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das2022-04-281-0/+12
View Lorry Controller Status