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delta/linux-next.git
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baserock/edcragg/armv8l-tegra-jetson-tx1-support
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path:
root
/
drivers
/
clk
/
renesas
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
|
clk: renesas: r9a06g032: Fix the RTC hclock description
Miquel Raynal
2022-04-28
1
-1
/
+1
*
|
clk: renesas: r8a779f0: Add UFS clock
Yoshihiro Shimoda
2022-04-25
1
-0
/
+1
*
|
clk: renesas: r9a07g043: Add SDHI clock and reset entries
Biju Das
2022-04-13
1
-0
/
+35
*
|
clk: renesas: r9a07g043: Add GbEthernet clock/reset
Biju Das
2022-04-13
1
-0
/
+10
*
|
clk: renesas: r9a07g043: Add ethernet clock sources
Biju Das
2022-04-13
1
-0
/
+13
*
|
clk: renesas: r9a07g043: Add GPIO clock and reset entries
Biju Das
2022-04-13
1
-0
/
+5
*
|
clk: renesas: Add support for RZ/G2UL SoC
Biju Das
2022-04-13
5
-1
/
+171
*
|
clk: renesas: Move RPC core clocks
Geert Uytterhoeven
2022-04-13
12
-57
/
+51
*
|
clk: renesas: rzg2l: Simplify multiplication/shift logic
Geert Uytterhoeven
2022-04-13
1
-1
/
+1
*
|
clk: renesas: r8a77995: Add RPC clocks
Geert Uytterhoeven
2022-04-11
2
-1
/
+13
*
|
clk: renesas: r8a77990: Add RPC clocks
Geert Uytterhoeven
2022-04-11
1
-0
/
+9
*
|
clk: renesas: rzg2l: Remove unused notifiers
Phil Edworthy
2022-04-04
1
-2
/
+0
|
/
*
clk: renesas: r8a779f0: Add PFC clock
Geert Uytterhoeven
2022-02-22
1
-0
/
+1
*
clk: renesas: r8a779f0: Add I2C clocks
Geert Uytterhoeven
2022-02-22
1
-0
/
+6
*
clk: renesas: r8a779f0: Add WDT clock
Geert Uytterhoeven
2022-02-22
1
-0
/
+9
*
clk: renesas: r8a779f0: Fix RSW2 clock divider
Geert Uytterhoeven
2022-02-22
1
-1
/
+1
*
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
Biju Das
2022-02-10
5
-191
/
+250
*
clk: renesas: r8a779a0: Add CANFD module clock
Ulrich Hecht
2022-01-24
1
-0
/
+1
*
clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
Lad Prabhakar
2022-01-24
1
-2
/
+2
*
clk: renesas: r8a7799[05]: Add MLP clocks
Nikita Yushchenko
2022-01-24
2
-0
/
+2
*
clk: renesas: r8a779f0: Add SYS-DMAC clocks
Yoshihiro Shimoda
2022-01-24
1
-0
/
+2
*
clk: renesas: r9a07g044: Add GPU clock and reset entries
Biju Das
2021-12-08
1
-0
/
+9
*
clk: renesas: r9a07g044: Add mux and divider for G clock
Biju Das
2021-12-08
2
-0
/
+10
*
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
Biju Das
2021-12-08
1
-2
/
+2
*
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Yoshihiro Shimoda
2021-12-08
5
-0
/
+196
*
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
Yoshihiro Shimoda
2021-12-08
7
-341
/
+437
*
clk: renesas: r9a07g044: Add TSU clock and reset entry
Biju Das
2021-11-26
1
-0
/
+3
*
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
Lad Prabhakar
2021-11-19
1
-2
/
+1
*
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
Lad Prabhakar
2021-11-19
1
-1
/
+14
*
clk: renesas: rzg2l: propagate return value of_genpd_add_provider_simple()
Lad Prabhakar
2021-11-19
1
-2
/
+1
*
clk: renesas: rzg2l: Check return value of pm_genpd_init()
Lad Prabhakar
2021-11-19
1
-1
/
+13
*
clk: renesas: r9a07g044: Add RSPI clock and reset entries
Lad Prabhakar
2021-11-19
1
-0
/
+9
*
clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV
Biju Das
2021-11-19
1
-1
/
+10
*
clk: renesas: rzg2l: Add CPG_PL1_DDIV macro
Biju Das
2021-11-19
1
-0
/
+2
*
clk: renesas: rcar-gen3: Remove outdated SD_SKIP_FIRST
Wolfram Sang
2021-11-19
1
-12
/
+3
*
clk: renesas: rcar-gen3: Switch to new SD clock handling
Wolfram Sang
2021-11-19
4
-202
/
+32
*
clk: renesas: r8a779a0: Add SDnH clock to V3U
Wolfram Sang
2021-11-19
1
-1
/
+10
*
clk: renesas: rcar-gen3: Add SDnH clock
Wolfram Sang
2021-11-19
10
-32
/
+64
*
clk: renesas: rcar-gen3: Add dummy SDnH clock
Wolfram Sang
2021-11-19
4
-0
/
+21
*
clk: renesas: r9a07g044: Add OSTM clock and reset entries
Biju Das
2021-11-15
1
-0
/
+9
*
clk: renesas: r9a07g044: Rename CLK_PLL2_DIV16 and CLK_PLL2_DIV20 macros
Biju Das
2021-11-15
1
-6
/
+6
*
clk: renesas: r9a07g044: Add WDT clock and reset entries
Biju Das
2021-11-15
1
-0
/
+15
*
clk: renesas: r9a07g044: Add clock and reset entry for SCI1
Lad Prabhakar
2021-11-15
1
-0
/
+3
*
clk: renesas: rzg2l: Add missing kerneldoc for resets
Geert Uytterhoeven
2021-11-15
2
-0
/
+4
*
clk: renesas: r8a779[56]x: Add MLP clocks
Andrey Gusakov
2021-10-15
3
-0
/
+3
*
clk: renesas: r9a07g044: Add SDHI clock and reset entries
Biju Das
2021-10-08
2
-0
/
+40
*
clk: renesas: rzg2l: Add SDHI clk mux support
Biju Das
2021-10-08
2
-0
/
+130
*
clk: renesas: r8a779a0: Add RPC support
Wolfram Sang
2021-10-08
1
-0
/
+32
*
clk: renesas: cpg-lib: Move RPC clock registration to the library
Wolfram Sang
2021-10-08
3
-87
/
+92
*
clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Co...
Lad Prabhakar
2021-10-08
2
-0
/
+21
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