| Commit message (Expand) | Author | Age | Files | Lines |
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| * | clk: rockchip: fix i2s gate bits on rk3066 and rk3188 | Johan Jonker | 2020-11-29 | 1 | -3/+4 |
| * | clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks | Johan Jonker | 2020-11-29 | 1 | -14/+14 |
| * | clk: rockchip: Remove redundant null check before clk_prepare_enable | Xu Wang | 2020-11-29 | 1 | -2/+1 |
| * | clk: rockchip: Add appropriate arch dependencies | Robin Murphy | 2020-10-26 | 1 | -1/+11 |
| * | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2020-10-22 | 8 | -85/+231 |
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| | * | clk: rockchip: Initialize hw to error to avoid undefined behavior | Stephen Boyd | 2020-10-07 | 1 | -1/+1 |
| | * | clk: rockchip: rk3399: Support module build | Elaine Zhang | 2020-09-22 | 2 | -1/+57 |
| | * | clk: rockchip: fix the clk config to support module build | Elaine Zhang | 2020-09-22 | 2 | -20/+100 |
| | * | clk: rockchip: Export some clock common APIs for module drivers | Elaine Zhang | 2020-09-22 | 1 | -22/+30 |
| | * | clk: rockchip: Export rockchip_register_softrst() | Elaine Zhang | 2020-09-22 | 1 | -3/+4 |
| | * | clk: rockchip: Export rockchip_clk_register_ddrclk() | Elaine Zhang | 2020-09-22 | 1 | -0/+1 |
| | * | clk: rockchip: Use clk_hw_register_composite instead of clk_register_composit... | Elaine Zhang | 2020-09-22 | 2 | -39/+40 |
| | * | clk: rockchip: rk3308: drop unused mux_timer_src_p | Krzysztof Kozlowski | 2020-09-22 | 1 | -1/+0 |
| * | | clk: rockchip: Fix initialization of mux_pll_src_4plls_p | Nathan Chancellor | 2020-08-18 | 1 | -1/+1 |
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| * | clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks | Alex Bee | 2020-07-22 | 1 | -0/+1 |
| * | clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" | Robin Murphy | 2020-07-08 | 1 | -4/+4 |
| * | clk: rockchip: use separate compatibles for rk3288w-cru | Heiko Stuebner | 2020-07-05 | 1 | -2/+19 |
| * | clk: rockchip: Handle clock tree for rk3288w variant | Mylène Josserand | 2020-06-17 | 1 | -2/+18 |
| * | clk: rockchip: convert rk3036 pll type to use internal lock status | Heiko Stuebner | 2020-06-15 | 1 | -3/+23 |
| * | clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout | Heiko Stuebner | 2020-06-15 | 1 | -15/+6 |
| * | clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout | Heiko Stuebner | 2020-06-15 | 1 | -11/+12 |
| * | clk: rockchip: fix incorrect configuration of rk3228 aclk_gpu* clocks | Justin Swartz | 2020-04-13 | 1 | -13/+4 |
| * | clk: rockchip: fix mmc get phase | Jerome Brunet | 2020-03-06 | 1 | -2/+2 |
| * | clk: let init callback return an error code | Jerome Brunet | 2019-12-23 | 1 | -11/+17 |
| * | clk: rockchip: protect the pclk_usb_grf as critical on px30 | Heiko Stuebner | 2019-11-05 | 1 | -1/+2 |
| * | clk: rockchip: add video-related niu clocks as critical on px30 | Heiko Stuebner | 2019-11-05 | 1 | -5/+10 |
| * | clk: rockchip: move px30 critical clocks to correct clock controller | Heiko Stuebner | 2019-11-05 | 1 | -4/+4 |
| * | clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc | Finley Xiao | 2019-11-05 | 1 | -4/+40 |
| * | clk: rockchip: make clk_half_divider_ops static | Ben Dooks (Codethink) | 2019-10-31 | 1 | -2/+1 |
| * | clk: rockchip: Add clock controller for the rk3308 | Finley Xiao | 2019-09-05 | 3 | -0/+969 |
| * | clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver | Nathan Huckleberry | 2019-07-25 | 1 | -1/+0 |
| * | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2019-07-17 | 8 | -46/+27 |
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| | * | clk: rockchip: export HDMIPHY clock on rk3228 | Heiko Stuebner | 2019-06-27 | 1 | -1/+1 |
| | * | clk: rockchip: add watchdog pclk on rk3328 | Heiko Stuebner | 2019-06-27 | 1 | -0/+3 |
| | * | clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro | Heiko Stuebner | 2019-06-15 | 4 | -36/+12 |
| | * | clk: rockchip: add a type from SGRF-controlled gate clocks | Heiko Stuebner | 2019-06-14 | 1 | -0/+4 |
| | * | clk: rockchip: Remove 48 MHz PLL rate from rk3288 | Douglas Anderson | 2019-06-06 | 1 | -1/+0 |
| | * | clk: rockchip: add 1.464GHz cpu-clock rate to rk3228 | Justin Swartz | 2019-05-20 | 1 | -0/+1 |
| | * | clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase() | Douglas Anderson | 2019-05-20 | 1 | -3/+3 |
| | * | clk: rockchip: Don't yell about bad mmc phases when getting | Douglas Anderson | 2019-05-20 | 1 | -3/+1 |
| | * | clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation | Douglas Anderson | 2019-05-20 | 1 | -2/+2 |
| * | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner | 2019-06-19 | 1 | -4/+1 |
| * | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner | 2019-06-05 | 1 | -11/+1 |
| * | | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 | Thomas Gleixner | 2019-05-30 | 17 | -170/+17 |
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| * | clk: Remove io.h from clk-provider.h | Stephen Boyd | 2019-05-15 | 12 | -1/+13 |
| *-. | Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' a... | Stephen Boyd | 2019-05-07 | 4 | -26/+60 |
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| | | * | clk: rockchip: undo several noc and special clocks as critical on rk3288 | Douglas Anderson | 2019-04-23 | 1 | -9/+4 |
| | | * | clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type | Finley Xiao | 2019-04-12 | 2 | -3/+29 |
| | | * | clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 | Douglas Anderson | 2019-04-12 | 1 | -0/+11 |
| | | * | clk: rockchip: Limit use of USB PHY clock to USB on rk3288 | Matthias Kaehlcke | 2019-04-12 | 1 | -2/+2 |
