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path: root/drivers/gpu/drm/i915/i915_reg.h
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* drm/i915/perf: fix whitelist on Gen10+Lionel Landwerlin2019-06-121-0/+1
* Merge tag 'drm-intel-fixes-2019-06-03' of git://anongit.freedesktop.org/drm/d...Dave Airlie2019-06-061-0/+3
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| * drm/i915/icl: Add WaDisableBankHangModeTvrtko Ursulin2019-05-291-0/+3
* | drm/i915: Maintain consistent documentation subsection orderingJonathan Corbet2019-05-241-3/+3
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* drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registersPaulo Zanoni2019-04-161-4/+4
* drm/i915: Handle catastrophic error on engine resetMika Kuoppala2019-04-121-2/+4
* drm/i915: Use Engine1 instance for gen11 pm interruptsMika Kuoppala2019-04-111-0/+5
* drm/i915/icl: Enable media sampler powergateMika Kuoppala2019-04-111-2/+3
* drm/i915: Remove unused VLV/CHV PSR registersJosé Roberto de Souza2019-04-081-36/+0
* drm/i915: Make RING_PDP relative to engine->mmio_baseChris Wilson2019-04-051-2/+2
* drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä2019-04-031-0/+4
* drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä2019-04-031-0/+9
* drm/i915: Don't use split gamma when we don't have toVille Syrjälä2019-04-031-0/+2
* drm/i915: Program EXT2 GC MAX registersUma Shankar2019-03-291-0/+1
* drm/i915/icl: Fix VEBOX mismatch BUG_ON()José Roberto de Souza2019-03-271-1/+1
* drm/i915: take a reference to uncore in the engine and use itDaniele Ceraolo Spurio2019-03-261-8/+8
* drm/i915: Use __is_constexpr()Chris Wilson2019-03-211-2/+2
* drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macroManasi Navare2019-03-201-1/+1
* drm/i915: Fix readout for cnl DPLL kdiv==3Ville Syrjälä2019-03-191-1/+1
* drm/i915: use REG_FIELD_PREP() to define register bitfield valuesJani Nikula2019-03-181-30/+39
* drm/i915: deprecate _SHIFT in favor of _MASK passed to accessorsJani Nikula2019-03-181-15/+30
* drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contentsJani Nikula2019-03-181-33/+61
* drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1José Roberto de Souza2019-03-131-0/+1
* Merge tag 'topic/hdr-formats-2019-03-07' of git://anongit.freedesktop.org/drm...Joonas Lahtinen2019-03-111-0/+9
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| * drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitionsSwati Sharma2019-03-051-0/+6
| * drm/i915: Add P010, P012, P016 plane control definitionsJuha-Pekka Heikkila2019-03-051-0/+3
* | drm/i915/icl: Fix CRC mismatch error for DP link layer complianceAditya Swarup2019-03-111-6/+7
* | drm/i915: Read out memory typeVille Syrjälä2019-03-071-0/+13
* | drm/i915: Extract DIMM info on cnl+Ville Syrjälä2019-03-071-2/+15
* | drm/i915: Fix DRAM size reporting for BXTVille Syrjälä2019-03-071-5/+5
* | drm/i915: Store the BIT(engine->id) as the engine's maskChris Wilson2019-03-051-12/+12
* | drm/i915: Fix bit name in PP_STATUS registerLucas De Marchi2019-03-041-1/+1
* | drm/i915: Add the missing HDMI gamut metadata packet stuffVille Syrjälä2019-02-261-3/+5
* | drm/i915/icl: Drop redundant gamma mode maskUma Shankar2019-02-211-1/+0
* | drm/i915: Extend skl+ crc sources with more planesVille Syrjälä2019-02-201-0/+9
* | drm/i915: Include "ignore lines" in skl+ wm stateVille Syrjälä2019-02-141-0/+1
* | Revert "drm/i915: W/A for underruns with WM1+ disabled on icl"Ville Syrjälä2019-02-141-1/+0
* | drm/i915: Make MG PHY macros semantically consistentAditya Swarup2019-02-141-25/+25
* | drm/i915: Make combo PHY DDI macro definitions consistent for ICL and CNLAditya Swarup2019-02-141-3/+3
* | drm/i915: Assert that VED and ISP are power gatedVille Syrjälä2019-02-131-0/+28
* | drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/Ville Syrjälä2019-02-131-1/+1
* | drm/i915/icl: Enable pipe output cscUma Shankar2019-02-131-0/+65
* | drm/i915/icl: Enable ICL Pipe CSC blockUma Shankar2019-02-131-3/+6
* | drm/i915/icl: Add icl pipe degamma and gamma supportUma Shankar2019-02-131-5/+7
* | drm/i915: Track pipe csc enable in crtc stateVille Syrjälä2019-02-081-2/+2
* | drm/i915: Populate gamma_mode for all platformsVille Syrjälä2019-02-081-2/+8
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* drm/i915: Just use icl+ definition for PLANE_WM blocks fieldVille Syrjälä2019-02-061-2/+1
* drm/i915: Bump skl+ wm blocks to 11 bitsVille Syrjälä2019-02-061-1/+1
* drm/i915: W/A for underruns with WM1+ disabled on iclVille Syrjälä2019-02-051-0/+1
* drm/i915/icl: restore WaEnableFloatBlendOptimizationTalha Nassar2019-02-011-0/+3
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