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| author | Michael Shych <michaelsh@mellanox.com> | 2020-05-04 17:14:27 +0300 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@linux-watchdog.org> | 2020-08-05 18:42:45 +0200 |
| commit | d6e6d5627f0aaa16d6b6e94238d62a594a35b5ce (patch) | |
| tree | 1a2658425fb4fcdb08795ba05f45c62eed28cdfb | |
| parent | eee851143bca4422eeee3bb2e104b85537ba449d (diff) | |
| download | linux-rt-d6e6d5627f0aaa16d6b6e94238d62a594a35b5ce.tar.gz | |
docs: watchdog: mlx-wdt: Add description of new watchdog type 3
Add documentation with details of new type of Mellanox watchdog driver.
Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Reviewed-by: Vadim Pasternak <vadimp@mellanox.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20200504141427.17685-5-michaelsh@mellanox.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
| -rw-r--r-- | Documentation/watchdog/mlx-wdt.rst | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/watchdog/mlx-wdt.rst b/Documentation/watchdog/mlx-wdt.rst index bf5bafac47f0..35e690dea9db 100644 --- a/Documentation/watchdog/mlx-wdt.rst +++ b/Documentation/watchdog/mlx-wdt.rst @@ -24,10 +24,19 @@ Type 2: Maximum timeout is 255 sec. Get time-left is supported. +Type 3: + Same as Type 2 with extended maximum timeout period. + Maximum timeout is 65535 sec. + Type 1 HW watchdog implementation exist in old systems and all new systems have type 2 HW watchdog. Two types of HW implementation have also different register map. +Type 3 HW watchdog implementation can exist on all Mellanox systems +with new programmer logic device. +It's differentiated by WD capability bit. +Old systems still have only one main watchdog. + Mellanox system can have 2 watchdogs: main and auxiliary. Main and auxiliary watchdog devices can be enabled together on the same system. @@ -54,3 +63,4 @@ The driver checks during initialization if the previous system reset was done by the watchdog. If yes, it makes a notification about this event. Access to HW registers is performed through a generic regmap interface. +Programmable logic device registers have little-endian order. |