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| author | Stephen Boyd <sboyd@codeaurora.org> | 2016-03-01 17:26:48 -0800 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2016-07-12 08:48:02 -0400 |
| commit | d9d898db8e45b25a3293c98317fbcdc2ed5f8adc (patch) | |
| tree | 3f58ba2374bcc12e7321c54a842d3c22e4c8d05c | |
| parent | be75dcc0a08c5816df3cb21281b2e399f5e656b2 (diff) | |
| download | linux-rt-d9d898db8e45b25a3293c98317fbcdc2ed5f8adc.tar.gz | |
clk: qcom: msm8960: Fix ce3_src register offset
[ Upstream commit 0f75e1a370fd843c9e508fc1ccf0662833034827 ]
The offset seems to have been copied from the sata clk. Fix it so
that enabling the crypto engine source clk works.
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index 5e3af78bf71b..9004a4e88800 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2740,7 +2740,7 @@ static struct clk_rcg ce3_src = { }, .freq_tbl = clk_tbl_ce3, .clkr = { - .enable_reg = 0x2c08, + .enable_reg = 0x36c0, .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "ce3_src", |