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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2016-03-23 19:08:20 +0800 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2016-05-04 09:58:04 +0100 |
| commit | b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 (patch) | |
| tree | 9072b01dd90206a5908274e8d91337c1ca41badf /Documentation/memory-barriers.txt | |
| parent | 5e79cb29ddbd1d354398308309337ba013245469 (diff) | |
| download | linux-rt-b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43.tar.gz | |
irqchip: Add Layerscape SCFG MSI controller support
Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation/memory-barriers.txt')
0 files changed, 0 insertions, 0 deletions