diff options
Diffstat (limited to 'drivers/gpu/drm/mgag200')
| -rw-r--r-- | drivers/gpu/drm/mgag200/Kconfig | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/mgag200/mgag200_drv.c | 227 | ||||
| -rw-r--r-- | drivers/gpu/drm/mgag200/mgag200_drv.h | 19 | ||||
| -rw-r--r-- | drivers/gpu/drm/mgag200/mgag200_mm.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/mgag200/mgag200_mode.c | 153 | ||||
| -rw-r--r-- | drivers/gpu/drm/mgag200/mgag200_reg.h | 4 |
6 files changed, 341 insertions, 82 deletions
diff --git a/drivers/gpu/drm/mgag200/Kconfig b/drivers/gpu/drm/mgag200/Kconfig index 93be766715c9..eec59658a938 100644 --- a/drivers/gpu/drm/mgag200/Kconfig +++ b/drivers/gpu/drm/mgag200/Kconfig @@ -1,13 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only config DRM_MGAG200 - tristate "Kernel modesetting driver for MGA G200 server engines" + tristate "Matrox G200" depends on DRM && PCI && MMU select DRM_GEM_SHMEM_HELPER select DRM_KMS_HELPER help - This is a KMS driver for the MGA G200 server chips, it - does not support the original MGA G200 or any of the desktop - chips. It requires 0.3.0 of the modesetting userspace driver, - and a version of mga driver that will fail on KMS enabled - devices. - + This is a KMS driver for Matrox G200 chips. It supports the original + MGA G200 desktop chips and the server variants. It requires 0.3.0 + of the modesetting userspace driver, and a version of mga driver + that will fail on KMS enabled devices. diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.c b/drivers/gpu/drm/mgag200/mgag200_drv.c index e19660f4a637..771b26aeee19 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.c +++ b/drivers/gpu/drm/mgag200/mgag200_drv.c @@ -9,6 +9,7 @@ #include <linux/console.h> #include <linux/module.h> #include <linux/pci.h> +#include <linux/vmalloc.h> #include <drm/drm_drv.h> #include <drm/drm_file.h> @@ -36,6 +37,7 @@ static struct drm_driver mgag200_driver = { .major = DRIVER_MAJOR, .minor = DRIVER_MINOR, .patchlevel = DRIVER_PATCHLEVEL, + .gem_create_object = drm_gem_shmem_create_object_cached, DRM_GEM_SHMEM_DRIVER_OPS, }; @@ -43,18 +45,66 @@ static struct drm_driver mgag200_driver = { * DRM device */ -static int mgag200_device_init(struct mga_device *mdev, unsigned long flags) +static bool mgag200_has_sgram(struct mga_device *mdev) { struct drm_device *dev = &mdev->base; - int ret, option; + u32 option; + int ret; - mdev->flags = mgag200_flags_from_driver_data(flags); - mdev->type = mgag200_type_from_driver_data(flags); + ret = pci_read_config_dword(dev->pdev, PCI_MGA_OPTION, &option); + if (drm_WARN(dev, ret, "failed to read PCI config dword: %d\n", ret)) + return false; - pci_read_config_dword(dev->pdev, PCI_MGA_OPTION, &option); - mdev->has_sdram = !(option & (1 << 14)); + return !!(option & PCI_MGA_OPTION_HARDPWMSK); +} - /* BAR 0 is the framebuffer, BAR 1 contains registers */ +static int mgag200_regs_init(struct mga_device *mdev) +{ + struct drm_device *dev = &mdev->base; + u32 option, option2; + u8 crtcext3; + + switch (mdev->type) { + case G200_PCI: + case G200_AGP: + if (mgag200_has_sgram(mdev)) + option = 0x4049cd21; + else + option = 0x40499121; + option2 = 0x00008000; + break; + case G200_SE_A: + case G200_SE_B: + option = 0x40049120; + if (mgag200_has_sgram(mdev)) + option |= PCI_MGA_OPTION_HARDPWMSK; + option2 = 0x00008000; + break; + case G200_WB: + case G200_EW3: + option = 0x41049120; + option2 = 0x0000b000; + break; + case G200_EV: + option = 0x00000120; + option2 = 0x0000b000; + break; + case G200_EH: + case G200_EH3: + option = 0x00000120; + option2 = 0x0000b000; + break; + default: + option = 0; + option2 = 0; + } + + if (option) + pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); + if (option2) + pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); + + /* BAR 1 contains registers */ mdev->rmmio_base = pci_resource_start(dev->pdev, 1); mdev->rmmio_size = pci_resource_len(dev->pdev, 1); @@ -68,12 +118,163 @@ static int mgag200_device_init(struct mga_device *mdev, unsigned long flags) if (mdev->rmmio == NULL) return -ENOMEM; - /* stash G200 SE model number for later use */ - if (IS_G200_SE(mdev)) { - mdev->unique_rev_id = RREG32(0x1e24); - drm_dbg(dev, "G200 SE unique revision id is 0x%x\n", - mdev->unique_rev_id); + RREG_ECRT(0x03, crtcext3); + crtcext3 |= MGAREG_CRTCEXT3_MGAMODE; + WREG_ECRT(0x03, crtcext3); + + return 0; +} + +static void mgag200_g200_interpret_bios(struct mga_device *mdev, + const unsigned char *bios, + size_t size) +{ + static const char matrox[] = {'M', 'A', 'T', 'R', 'O', 'X'}; + static const unsigned int expected_length[6] = { + 0, 64, 64, 64, 128, 128 + }; + struct drm_device *dev = &mdev->base; + const unsigned char *pins; + unsigned int pins_len, version; + int offset; + int tmp; + + /* Test for MATROX string. */ + if (size < 45 + sizeof(matrox)) + return; + if (memcmp(&bios[45], matrox, sizeof(matrox)) != 0) + return; + + /* Get the PInS offset. */ + if (size < MGA_BIOS_OFFSET + 2) + return; + offset = (bios[MGA_BIOS_OFFSET + 1] << 8) | bios[MGA_BIOS_OFFSET]; + + /* Get PInS data structure. */ + + if (size < offset + 6) + return; + pins = bios + offset; + if (pins[0] == 0x2e && pins[1] == 0x41) { + version = pins[5]; + pins_len = pins[2]; + } else { + version = 1; + pins_len = pins[0] + (pins[1] << 8); + } + + if (version < 1 || version > 5) { + drm_warn(dev, "Unknown BIOS PInS version: %d\n", version); + return; + } + if (pins_len != expected_length[version]) { + drm_warn(dev, "Unexpected BIOS PInS size: %d expected: %d\n", + pins_len, expected_length[version]); + return; } + if (size < offset + pins_len) + return; + + drm_dbg_kms(dev, "MATROX BIOS PInS version %d size: %d found\n", + version, pins_len); + + /* Extract the clock values */ + + switch (version) { + case 1: + tmp = pins[24] + (pins[25] << 8); + if (tmp) + mdev->model.g200.pclk_max = tmp * 10; + break; + case 2: + if (pins[41] != 0xff) + mdev->model.g200.pclk_max = (pins[41] + 100) * 1000; + break; + case 3: + if (pins[36] != 0xff) + mdev->model.g200.pclk_max = (pins[36] + 100) * 1000; + if (pins[52] & 0x20) + mdev->model.g200.ref_clk = 14318; + break; + case 4: + if (pins[39] != 0xff) + mdev->model.g200.pclk_max = pins[39] * 4 * 1000; + if (pins[92] & 0x01) + mdev->model.g200.ref_clk = 14318; + break; + case 5: + tmp = pins[4] ? 8000 : 6000; + if (pins[123] != 0xff) + mdev->model.g200.pclk_min = pins[123] * tmp; + if (pins[38] != 0xff) + mdev->model.g200.pclk_max = pins[38] * tmp; + if (pins[110] & 0x01) + mdev->model.g200.ref_clk = 14318; + break; + default: + break; + } +} + +static void mgag200_g200_init_refclk(struct mga_device *mdev) +{ + struct drm_device *dev = &mdev->base; + unsigned char __iomem *rom; + unsigned char *bios; + size_t size; + + mdev->model.g200.pclk_min = 50000; + mdev->model.g200.pclk_max = 230000; + mdev->model.g200.ref_clk = 27050; + + rom = pci_map_rom(dev->pdev, &size); + if (!rom) + return; + + bios = vmalloc(size); + if (!bios) + goto out; + memcpy_fromio(bios, rom, size); + + if (size != 0 && bios[0] == 0x55 && bios[1] == 0xaa) + mgag200_g200_interpret_bios(mdev, bios, size); + + drm_dbg_kms(dev, "pclk_min: %ld pclk_max: %ld ref_clk: %ld\n", + mdev->model.g200.pclk_min, mdev->model.g200.pclk_max, + mdev->model.g200.ref_clk); + + vfree(bios); +out: + pci_unmap_rom(dev->pdev, rom); +} + +static void mgag200_g200se_init_unique_id(struct mga_device *mdev) +{ + struct drm_device *dev = &mdev->base; + + /* stash G200 SE model number for later use */ + mdev->model.g200se.unique_rev_id = RREG32(0x1e24); + + drm_dbg(dev, "G200 SE unique revision id is 0x%x\n", + mdev->model.g200se.unique_rev_id); +} + +static int mgag200_device_init(struct mga_device *mdev, unsigned long flags) +{ + struct drm_device *dev = &mdev->base; + int ret; + + mdev->flags = mgag200_flags_from_driver_data(flags); + mdev->type = mgag200_type_from_driver_data(flags); + + ret = mgag200_regs_init(mdev); + if (ret) + return ret; + + if (mdev->type == G200_PCI || mdev->type == G200_AGP) + mgag200_g200_init_refclk(mdev); + else if (IS_G200_SE(mdev)) + mgag200_g200se_init_unique_id(mdev); ret = mgag200_mm_init(mdev); if (ret) @@ -116,6 +317,8 @@ mgag200_device_create(struct pci_dev *pdev, unsigned long flags) */ static const struct pci_device_id mgag200_pciidlist[] = { + { PCI_VENDOR_ID_MATROX, 0x520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, G200_PCI }, + { PCI_VENDOR_ID_MATROX, 0x521, PCI_ANY_ID, PCI_ANY_ID, 0, 0, G200_AGP }, { PCI_VENDOR_ID_MATROX, 0x522, PCI_ANY_ID, PCI_ANY_ID, 0, 0, G200_SE_A | MGAG200_FLAG_HW_BUG_NO_STARTADD}, { PCI_VENDOR_ID_MATROX, 0x524, PCI_ANY_ID, PCI_ANY_ID, 0, 0, G200_SE_B }, diff --git a/drivers/gpu/drm/mgag200/mgag200_drv.h b/drivers/gpu/drm/mgag200/mgag200_drv.h index 3817520bfefc..749a075fe9e4 100644 --- a/drivers/gpu/drm/mgag200/mgag200_drv.h +++ b/drivers/gpu/drm/mgag200/mgag200_drv.h @@ -38,6 +38,8 @@ #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg)) #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg)) +#define MGA_BIOS_OFFSET 0x7ffc + #define ATTR_INDEX 0x1fc0 #define ATTR_DATA 0x1fc1 @@ -129,6 +131,8 @@ struct mga_mc { }; enum mga_type { + G200_PCI, + G200_AGP, G200_SE_A, G200_SE_B, G200_WB, @@ -161,14 +165,23 @@ struct mga_device { size_t vram_fb_available; enum mga_type type; - int has_sdram; int bpp_shifts[4]; int fb_mtrr; - /* SE model number stored in reg 0x1e24 */ - u32 unique_rev_id; + union { + struct { + long ref_clk; + long pclk_min; + long pclk_max; + } g200; + struct { + /* SE model number stored in reg 0x1e24 */ + u32 unique_rev_id; + } g200se; + } model; + struct mga_connector connector; struct drm_simple_display_pipe display_pipe; diff --git a/drivers/gpu/drm/mgag200/mgag200_mm.c b/drivers/gpu/drm/mgag200/mgag200_mm.c index 7b69392bcb89..641f1aa992be 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mm.c +++ b/drivers/gpu/drm/mgag200/mgag200_mm.c @@ -90,9 +90,17 @@ static void mgag200_mm_release(struct drm_device *dev, void *ptr) int mgag200_mm_init(struct mga_device *mdev) { struct drm_device *dev = &mdev->base; + u8 misc; resource_size_t start, len; int ret; + WREG_ECRT(0x04, 0x00); + + misc = RREG8(MGA_MISC_IN); + misc |= MGAREG_MISC_RAMMAPEN | + MGAREG_MISC_HIGH_PG_SEL; + WREG8(MGA_MISC_OUT, misc); + /* BAR 0 is VRAM */ start = pci_resource_start(dev->pdev, 0); len = pci_resource_len(dev->pdev, 0); diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index e0d037a7413c..38672f9e5c4f 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -9,7 +9,6 @@ */ #include <linux/delay.h> -#include <linux/pci.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_state_helper.h> @@ -109,10 +108,82 @@ static inline void mga_wait_busy(struct mga_device *mdev) } while ((status & 0x01) && time_before(jiffies, timeout)); } +/* + * PLL setup + */ + +static int mgag200_g200_set_plls(struct mga_device *mdev, long clock) +{ + struct drm_device *dev = &mdev->base; + const int post_div_max = 7; + const int in_div_min = 1; + const int in_div_max = 6; + const int feed_div_min = 7; + const int feed_div_max = 127; + u8 testm, testn; + u8 n = 0, m = 0, p, s; + long f_vco; + long computed; + long delta, tmp_delta; + long ref_clk = mdev->model.g200.ref_clk; + long p_clk_min = mdev->model.g200.pclk_min; + long p_clk_max = mdev->model.g200.pclk_max; + + if (clock > p_clk_max) { + drm_err(dev, "Pixel Clock %ld too high\n", clock); + return 1; + } + + if (clock < p_clk_min >> 3) + clock = p_clk_min >> 3; + + f_vco = clock; + for (p = 0; + p <= post_div_max && f_vco < p_clk_min; + p = (p << 1) + 1, f_vco <<= 1) + ; + + delta = clock; + + for (testm = in_div_min; testm <= in_div_max; testm++) { + for (testn = feed_div_min; testn <= feed_div_max; testn++) { + computed = ref_clk * (testn + 1) / (testm + 1); + if (computed < f_vco) + tmp_delta = f_vco - computed; + else + tmp_delta = computed - f_vco; + if (tmp_delta < delta) { + delta = tmp_delta; + m = testm; + n = testn; + } + } + } + f_vco = ref_clk * (n + 1) / (m + 1); + if (f_vco < 100000) + s = 0; + else if (f_vco < 140000) + s = 1; + else if (f_vco < 180000) + s = 2; + else + s = 3; + + drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n", + clock, f_vco, m, n, p, s); + + WREG_DAC(MGA1064_PIX_PLLC_M, m); + WREG_DAC(MGA1064_PIX_PLLC_N, n); + WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3))); + + return 0; +} + #define P_ARRAY_SIZE 9 static int mga_g200se_set_plls(struct mga_device *mdev, long clock) { + u32 unique_rev_id = mdev->model.g200se.unique_rev_id; unsigned int vcomax, vcomin, pllreffreq; unsigned int delta, tmpdelta, permitteddelta; unsigned int testp, testm, testn; @@ -122,7 +193,7 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock) unsigned int fvv; unsigned int i; - if (mdev->unique_rev_id <= 0x03) { + if (unique_rev_id <= 0x03) { m = n = p = 0; vcomax = 320000; @@ -220,7 +291,7 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock) WREG_DAC(MGA1064_PIX_PLLC_N, n); WREG_DAC(MGA1064_PIX_PLLC_P, p); - if (mdev->unique_rev_id >= 0x04) { + if (unique_rev_id >= 0x04) { WREG_DAC(0x1a, 0x09); msleep(20); WREG_DAC(0x1a, 0x01); @@ -717,6 +788,9 @@ static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock) u8 misc; switch(mdev->type) { + case G200_PCI: + case G200_AGP: + return mgag200_g200_set_plls(mdev, clock); case G200_SE_A: case G200_SE_B: return mga_g200se_set_plls(mdev, clock); @@ -877,45 +951,6 @@ static void mgag200_set_startadd(struct mga_device *mdev, WREG_ECRT(0x00, crtcext0); } -static void mgag200_set_pci_regs(struct mga_device *mdev) -{ - uint32_t option = 0, option2 = 0; - struct drm_device *dev = &mdev->base; - - switch (mdev->type) { - case G200_SE_A: - case G200_SE_B: - if (mdev->has_sdram) - option = 0x40049120; - else - option = 0x4004d120; - option2 = 0x00008000; - break; - case G200_WB: - case G200_EW3: - option = 0x41049120; - option2 = 0x0000b000; - break; - case G200_EV: - option = 0x00000120; - option2 = 0x0000b000; - break; - case G200_EH: - case G200_EH3: - option = 0x00000120; - option2 = 0x0000b000; - break; - case G200_ER: - break; - } - - if (option) - pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); - - if (option2) - pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); -} - static void mgag200_set_dac_regs(struct mga_device *mdev) { size_t i; @@ -933,6 +968,12 @@ static void mgag200_set_dac_regs(struct mga_device *mdev) }; switch (mdev->type) { + case G200_PCI: + case G200_AGP: + dacvalue[MGA1064_SYS_PLL_M] = 0x04; + dacvalue[MGA1064_SYS_PLL_N] = 0x2D; + dacvalue[MGA1064_SYS_PLL_P] = 0x19; + break; case G200_SE_A: case G200_SE_B: dacvalue[MGA1064_VREF_CTL] = 0x03; @@ -986,9 +1027,8 @@ static void mgag200_set_dac_regs(struct mga_device *mdev) static void mgag200_init_regs(struct mga_device *mdev) { - u8 crtc11, crtcext3, crtcext4, misc; + u8 crtc11, misc; - mgag200_set_pci_regs(mdev); mgag200_set_dac_regs(mdev); WREG_SEQ(2, 0x0f); @@ -1002,14 +1042,6 @@ static void mgag200_init_regs(struct mga_device *mdev) WREG_CRT(14, 0); WREG_CRT(15, 0); - RREG_ECRT(0x03, crtcext3); - - crtcext3 |= BIT(7); /* enable MGA mode */ - crtcext4 = 0x00; - - WREG_ECRT(0x03, crtcext3); - WREG_ECRT(0x04, crtcext4); - RREG_CRT(0x11, crtc11); crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT | MGAREG_CRTC11_VINTEN | @@ -1023,9 +1055,7 @@ static void mgag200_init_regs(struct mga_device *mdev) WREG_ECRT(0x34, 0x5); misc = RREG8(MGA_MISC_IN); - misc |= MGAREG_MISC_IOADSEL | - MGAREG_MISC_RAMMAPEN | - MGAREG_MISC_HIGH_PG_SEL; + misc |= MGAREG_MISC_IOADSEL; WREG8(MGA_MISC_OUT, misc); } @@ -1234,12 +1264,13 @@ static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, const struct drm_display_mode *mode, const struct drm_framebuffer *fb) { + u32 unique_rev_id = mdev->model.g200se.unique_rev_id; unsigned int hiprilvl; u8 crtcext6; - if (mdev->unique_rev_id >= 0x04) { + if (unique_rev_id >= 0x04) { hiprilvl = 0; - } else if (mdev->unique_rev_id >= 0x02) { + } else if (unique_rev_id >= 0x02) { unsigned int bpp; unsigned long mb; @@ -1264,7 +1295,7 @@ static void mgag200_g200se_set_hiprilvl(struct mga_device *mdev, else hiprilvl = 5; - } else if (mdev->unique_rev_id >= 0x01) { + } else if (unique_rev_id >= 0x01) { hiprilvl = 3; } else { hiprilvl = 4; @@ -1388,7 +1419,9 @@ static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, int bpp = 32; if (IS_G200_SE(mdev)) { - if (mdev->unique_rev_id == 0x01) { + u32 unique_rev_id = mdev->model.g200se.unique_rev_id; + + if (unique_rev_id == 0x01) { if (mode->hdisplay > 1600) return MODE_VIRTUAL_X; if (mode->vdisplay > 1200) @@ -1396,7 +1429,7 @@ static enum drm_mode_status mga_vga_mode_valid(struct drm_connector *connector, if (mga_vga_calculate_mode_bandwidth(mode, bpp) > (24400 * 1024)) return MODE_BANDWIDTH; - } else if (mdev->unique_rev_id == 0x02) { + } else if (unique_rev_id == 0x02) { if (mode->hdisplay > 1920) return MODE_VIRTUAL_X; if (mode->vdisplay > 1200) diff --git a/drivers/gpu/drm/mgag200/mgag200_reg.h b/drivers/gpu/drm/mgag200/mgag200_reg.h index c3b7bcad52ed..977be0565c06 100644 --- a/drivers/gpu/drm/mgag200/mgag200_reg.h +++ b/drivers/gpu/drm/mgag200/mgag200_reg.h @@ -256,6 +256,8 @@ #define MGAREG_CRTCEXT1_VSYNCOFF BIT(5) #define MGAREG_CRTCEXT1_HSYNCOFF BIT(4) +#define MGAREG_CRTCEXT3_MGAMODE BIT(7) + /* Cursor X and Y position */ #define MGA_CURPOSXL 0x3c0c #define MGA_CURPOSXH 0x3c0d @@ -282,6 +284,8 @@ #define PCI_MGA_OPTION2 0x50 #define PCI_MGA_OPTION3 0x54 +#define PCI_MGA_OPTION_HARDPWMSK BIT(14) + #define RAMDAC_OFFSET 0x3c00 /* TVP3026 direct registers */ |