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* clk: samsung: exynos3250: Fix PLL ratesAndrzej Hajda2018-05-251-2/+2
* clk: samsung: exynos5250: Fix PLL ratesAndrzej Hajda2018-05-251-4/+4
* clk: samsung: exynos5433: Fix PLL ratesAndrzej Hajda2018-05-251-6/+6
* clk: samsung: exynos5260: Fix PLL ratesAndrzej Hajda2018-05-251-1/+1
* clk: samsung: exynos7: Fix PLL ratesAndrzej Hajda2018-05-251-1/+1
* clk: samsung: s3c2410: Fix PLL ratesAndrzej Hajda2018-05-251-8/+8
* clk: rockchip: Prevent calculating mmc phase if clock rate is zeroShawn Lin2018-05-251-0/+23
* clk: tegra: Fix pll_u rate configurationMarcel Ziswiler2018-05-251-0/+2
* clk: Don't show the incorrect clock phaseShawn Lin2018-05-251-0/+3
* clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228Shawn Lin2018-05-251-1/+1
* clk: bcm2835: De-assert/assert PLL reset signal when appropriateBoris Brezillon2018-04-241-3/+5
* clk: fix false-positive Wmaybe-uninitialized warningArnd Bergmann2018-04-241-3/+3
* clk: mvebu: armada-38x: add support for missing clocksRichard Genoud2018-04-241-7/+7
* clk: mvebu: armada-38x: add support for 1866MHz variantsRalph Sennhauser2018-04-241-3/+4
* clk: at91: fix clk-generated compilationAlexandre Belloni2018-04-131-0/+1
* clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2018-04-132-4/+7
* clk: Fix __set_clk_rates error print-stringBryan O'Donoghue2018-04-131-1/+1
* clk: scpi: fix return type of __scpi_dvfs_round_rateSudeep Holla2018-04-131-3/+3
* clk: at91: fix clk-generated parentingAlexandre Belloni2018-04-131-2/+1
* clk: renesas: rcar-gen2: Fix PLL0 on R-Car V2H and E2Geert Uytterhoeven2018-04-131-4/+19
* clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai2018-03-281-3/+3
* clk: bcm2835: Protect sections updating shared registersBoris Brezillon2018-03-281-0/+4
* clk: bcm2835: Fix ana->maskX definitionsBoris Brezillon2018-03-281-4/+4
* clk: migrate the count of orphaned clocks at initJerome Brunet2018-03-241-16/+21
* clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki2018-03-241-1/+1
* clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen2018-03-241-5/+24
* clk: Don't touch hardware when reparenting during registrationStephen Boyd2018-03-241-2/+5
* clk: ns2: Correct SDIO bitsBharat Kumar Reddy Gooty2018-03-241-1/+1
* clk: qcom: msm8916: fix mnd_width for codec_digcodecSrinivas Kandagatla2018-03-221-0/+1
* clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan2018-03-221-2/+2
* clk: qcom: msm8996: Fix the vfe1 powerdomain nameRajendra Nayak2018-03-221-1/+1
* clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery2018-02-251-0/+1
* clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERTobias Regnery2018-02-251-0/+1
* clk: sunxi: sun9i-mmc: Implement reset callback for reset controlsChen-Yu Tsai2017-12-291-0/+12
* clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collisionChen-Yu Tsai2017-12-251-1/+1
* clk: tegra: Fix cclk_lp divisor registerMichał Mirosław2017-12-201-1/+1
* clk: hi6220: mark clock cs_atb_syspll as criticalLeo Yan2017-12-201-1/+1
* clk: imx6: refine hdmi_isfr's parent to make HDMI work on i.MX6 SoCs w/o VPUSébastien Szymanski2017-12-201-1/+1
* clk: mediatek: add the option for determining PLL source clockChen Zhong2017-12-202-1/+5
* clk: uniphier: fix DAPLL2 clock rate of Pro5Masahiro Yamada2017-12-141-1/+1
* clk: qcom: ipq4019: Add all the frequencies for apss cpuAbhishek Sahu2017-11-301-2/+12
* clk: sunxi-ng: fix PLL_CPUX adjusting on A33Icenowy Zheng2017-11-301-0/+10
* clk: sunxi-ng: A31: Fix spdif clock registerMarcus Cooper2017-11-301-2/+2
* clk: ti: dra7-atl-clock: fix child-node lookupsJohan Hovold2017-11-301-2/+1
* clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni2017-11-151-5/+23
* clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski2017-11-151-2/+4
* clk: sunxi-ng: Check kzalloc() for errors and cleanup error pathStephen Boyd2017-11-081-0/+15
* clk/axs10x: Clear init field in driver probeJose Abreu2017-10-081-0/+1
* clk: sunxi-ng: fix PLL_CPUX adjusting on H3Ondrej Jirman2017-10-081-0/+10
* clk/samsung: exynos542x: mark some clocks as criticalMarek Szyprowski2017-08-111-7/+7
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