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path: root/drivers/gpu/drm/i915/intel_ddi.c
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* drm/i915: Don't use link_bw for PLL setupVille Syrjälä2015-09-011-7/+4
* drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi2015-08-261-50/+25
* drm/i915: Per-DDI I_boost overrideAntti Koskipaa2015-08-141-8/+30
* drm/i915: Set alternate aux for DDI-ERodrigo Vivi2015-08-141-3/+2
* drm/i915: set FDI translations to NULL on SKLPaulo Zanoni2015-07-061-0/+1
* drm/i915/bxt: BUNs related to port PLLVandana Kannan2015-07-061-10/+5
* drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä2015-07-061-25/+24
* drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak2015-07-031-0/+20
* drm/i915/bxt: add DDI port HW readout supportImre Deak2015-06-301-2/+20
* drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak2015-06-301-3/+13
* drm/i915/skl: Buffer translation improvementsDavid Weinehall2015-06-301-115/+394
* drm/i915/skl: Skip remaining dividers when deviation is 0Damien Lespiau2015-06-261-1/+8
* drm/i915/skl: Prefer even dividers for SKL DPLLsDamien Lespiau2015-06-261-0/+7
* drm/i915/skl: Replace the HDMI DPLL divider computation algorithmDamien Lespiau2015-06-261-74/+137
* drm/i915/bxt: fix DDI PHY vswing scale value settingImre Deak2015-06-121-18/+18
* drm/i915: Don't display the boot CDCLK twiceDamien Lespiau2015-06-121-4/+3
* drm/i915/bxt: edp1.4 Intermediate Freq supportSonika Jindal2015-06-031-23/+16
* drm/i915/skl: Don't try to store the wrong central frequencyDamien Lespiau2015-05-291-2/+0
* drm/i915: Correctly prefix HSW/BDW HDMI clock functionsDamien Lespiau2015-05-291-13/+12
* drm/i915/skl: Remove unnecessary () used with abs_diff()Damien Lespiau2015-05-291-1/+1
* drm/i915/skl: Remove unnecessary () used with div_u64()Damien Lespiau2015-05-291-3/+3
* drm/i915/skl: Factor out computing the DPLL paramaters from the dividersDamien Lespiau2015-05-291-64/+75
* drm/i915/skl: Use a more idomatic early returnDamien Lespiau2015-05-291-62/+59
* drm/i915/skl: Propagate the error if we fail to find a suitable DPLL dividerDamien Lespiau2015-05-291-2/+6
* drm/i915/skl: Display the WRPLL frequency we couldn't accomodate when failingDamien Lespiau2015-05-291-1/+2
* drm/i915/skl: Make sure to break when not finding suitable PLL dividersDamien Lespiau2015-05-291-0/+4
* drm/i915: remove useless DP and DDI encoder ->hot_plug hooksJani Nikula2015-05-291-15/+0
* drm/i915: group all hotplug related fields into a new struct in dev_privJani Nikula2015-05-291-1/+1
* drm/i915/skl: Deinit/init the display at suspend/resumeDamien Lespiau2015-05-211-2/+6
* drm/i915/bxt: Move around lane stagger calculationVandana Kannan2015-05-201-20/+20
* drm/i915/bxt: Port PLL programming BUNVandana Kannan2015-05-201-23/+56
* drm/i915: Don't overwrite (e)DP PLL selection on SKLAnder Conselvan de Oliveira2015-05-201-0/+9
* drm/i915/skl: Re-indent part of skl_ddi_calculate_wrpll()Damien Lespiau2015-05-081-32/+32
* drm/i915: Use for_each_connector_in_state helper macroAnder Conselvan de Oliveira2015-05-081-4/+5
* drm/i915/skl: Add module parameter to select edp vswing tableSonika Jindal2015-05-081-1/+1
* drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 definesDamien Lespiau2015-05-081-13/+13
* drm/i915: fix intel_prepare_ddiImre Deak2015-04-301-10/+18
* drm/i915: factor out ddi_get_encoder_portImre Deak2015-04-301-9/+19
* drm/i915/bxt: VSwing programming sequenceVandana Kannan2015-04-161-1/+119
* drm/i915: Don't write the HDMI buffer translation entry when not neededDamien Lespiau2015-04-161-0/+9
* drm/i915: Iterate through the initialized DDIs to prepare their buffersDamien Lespiau2015-04-161-4/+12
* drm/i915/bxt: Determine programmed frequencySatheeshakrishna M2015-04-161-1/+29
* drm/i915/bxt: Assign PLL for pipeSatheeshakrishna M2015-04-161-1/+1
* drm/i915/bxt: BXT clock divider calculationSatheeshakrishna M2015-04-161-0/+129
* drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequenceSatheeshakrishna M2015-04-161-0/+165
* drm/i915/bxt: Restrict PORT_CLK_SEL programming below gen9Satheeshakrishna M2015-04-161-2/+2
* drm/i915/skl: Add back HDMI translation tableSonika Jindal2015-04-161-10/+12
* drm/i915/bxt: add display initialize/uninitialize sequence (PHY)Vandana Kannan2015-04-161-0/+125
* drm/i915/bxt: add display initialize/uninitialize sequence (CDCLK)Vandana Kannan2015-04-161-0/+2
* Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter2015-04-141-1/+1
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