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| author | Andre Przywara <andre.przywara@arm.com> | 2023-03-20 00:52:46 +0000 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-03-27 22:45:22 +0200 |
| commit | a3eebcb61ffb9a26ca77a00ce80050cff0f0ecf3 (patch) | |
| tree | 8b5321e847179550c3aaafe686bad18b4b6e77b3 | |
| parent | cc1858614f5d99d87d4467079c25f6bdf434add9 (diff) | |
| download | linux-a3eebcb61ffb9a26ca77a00ce80050cff0f0ecf3.tar.gz | |
dts: add riscv include prefix link
The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical
die as their R528/T113-s siblings with ARM Cortex-A7 cores.
To allow sharing the basic SoC .dtsi files across those two
architectures as well, introduce a symlink to the RISC-V DT directory.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
| l--------- | scripts/dtc/include-prefixes/riscv | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv new file mode 120000 index 000000000000..202509418938 --- /dev/null +++ b/scripts/dtc/include-prefixes/riscv @@ -0,0 +1 @@ +../../../arch/riscv/boot/dts
\ No newline at end of file |