diff options
author | Dmitry Osipenko <digetx@gmail.com> | 2021-05-16 19:30:41 +0300 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2021-05-31 15:19:14 +0200 |
commit | c4a41429951890d0bf7c1ef49b1fa1c8dfb1a034 (patch) | |
tree | 19e114de705a997c963ca3f7b836f92936e0acf1 /Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt | |
parent | 6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff) | |
download | linux-c4a41429951890d0bf7c1ef49b1fa1c8dfb1a034.tar.gz |
dt-bindings: clock: tegra: Convert to schema
Convert NVIDIA Tegra clock bindings to schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt deleted file mode 100644 index 6c5901b503d0..000000000000 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ /dev/null @@ -1,63 +0,0 @@ -NVIDIA Tegra20 Clock And Reset Controller - -This binding uses the common clock binding: -Documentation/devicetree/bindings/clock/clock-bindings.txt - -The CAR (Clock And Reset) Controller on Tegra is the HW module responsible -for muxing and gating Tegra's clocks, and setting their rates. - -Required properties : -- compatible : Should be "nvidia,tegra20-car" -- reg : Should contain CAR registers location and length -- clocks : Should contain phandle and clock specifiers for two clocks: - the 32 KHz "32k_in", and the board-specific oscillator "osc". -- #clock-cells : Should be 1. - In clock consumers, this cell represents the clock ID exposed by the - CAR. The assignments may be found in header file - <dt-bindings/clock/tegra20-car.h>. -- #reset-cells : Should be 1. - In clock consumers, this cell represents the bit number in the CAR's - array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. - -Example SoC include file: - -/ { - tegra_car: clock { - compatible = "nvidia,tegra20-car"; - reg = <0x60006000 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - usb@c5004000 { - clocks = <&tegra_car TEGRA20_CLK_USB2>; - }; -}; - -Example board file: - -/ { - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - osc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - clk_32k: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - }; - - &tegra_car { - clocks = <&clk_32k> <&osc>; - }; -}; |