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authorQuentin Schulz <quentin.schulz@bootlin.com>2018-10-04 14:21:59 +0200
committerDavid S. Miller <davem@davemloft.net>2018-10-05 14:36:43 -0700
commit6afea95a80668b8e4fbde8ad21ba3949050e192f (patch)
tree2338dc4fa20c98245fc6a788470b53fc9e38f033 /Documentation/devicetree/bindings/mips
parent3df0e6804f0e36e347882789fcaf70cdac890707 (diff)
downloadlinux-6afea95a80668b8e4fbde8ad21ba3949050e192f.tar.gz
dt-bindings: net: ocelot: remove hsio from the list of register address spaces
HSIO register address space should be handled outside of the MAC controller as there are some registers for PLL5 configuring, SerDes/switch port muxing and a thermal sensor IP, so let's remove it. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree/bindings/mips')
-rw-r--r--Documentation/devicetree/bindings/mips/mscc.txt16
1 files changed, 16 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
index ae15ec333542..bc817e984628 100644
--- a/Documentation/devicetree/bindings/mips/mscc.txt
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -41,3 +41,19 @@ Example:
compatible = "mscc,ocelot-cpu-syscon", "syscon";
reg = <0x70000000 0x2c>;
};
+
+o HSIO regs:
+
+The SoC has a few registers (HSIO) handling miscellaneous functionalities:
+configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
+status, SerDes muxing and a thermal sensor.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@10d0000 {
+ compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
+ reg = <0x10d0000 0x10000>;
+ };