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| author | Brian Norris <briannorris@chromium.org> | 2016-12-16 16:59:16 -0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-12-19 13:29:27 +0000 |
| commit | 23e291c2e4c84a40a4b3de8539dec95bfda214f1 (patch) | |
| tree | 3416c6120ce48a4df0fbf716eeaee5af056d6faa /Documentation/devicetree/bindings/spi/spi-rockchip.txt | |
| parent | fafd67940774733fa97f4b09412aea6981b82e0a (diff) | |
| download | linux-23e291c2e4c84a40a4b3de8539dec95bfda214f1.tar.gz | |
spi: rockchip: support "sleep" pin configuration
In the pattern of many other devices, support a system-sleep pin
configuration.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-rockchip.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/spi-rockchip.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt index d2ca153614f9..83da4931d832 100644 --- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt +++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt @@ -31,6 +31,10 @@ Optional Properties: - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling Rx data (may need to be fine tuned for high capacitance lines). No delay (0) by default. +- pinctrl-names: Names for the pin configuration(s); may be "default" or + "sleep", where the "sleep" configuration may describe the state + the pins should be in during system suspend. See also + pinctrl/pinctrl-bindings.txt. Example: @@ -46,4 +50,7 @@ Example: interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; + pinctrl-0 = <&spi1_pins>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; }; |