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authorRajendra Nayak <rnayak@ti.com>2014-04-10 11:33:13 -0500
committerNishanth Menon <nm@ti.com>2014-05-05 14:34:26 -0500
commit53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad (patch)
tree1d74694608f7396918217c4efdde33157e1bd981 /Documentation
parentf33ddf745cbcd4145fcb2f8239f5dbba089fb8ff (diff)
downloadlinux-53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad.tar.gz
bus: omap_l3_noc: Add DRA7 interconnect error data
DRA7 is distinctly different from OMAP4 in terms of masters and clock domain organization. There two main clock domains which is divided as follows: <0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain <0x45000000 0x1000> is clk3 Add all the data needed to handle L3 error handling on DRA7 devices and mark clk2 as subdomain and provide a compatible flag for functionality. Other than the data difference the hardware blocks involved are essentially the same. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [nm@ti.com: bugfixes and generic improvements, documentation] Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/omap/l3-noc.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
index c0105de55cbd..45d0fc23de2d 100644
--- a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
+++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
@@ -6,6 +6,7 @@ provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
+ Should be "ti,dra7-l3-noc" for DRA7 family
- reg: Contains L3 register address range for each noc domain.
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.