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| author | Michael Witten <mfwitten@gmail.com> | 2011-07-15 03:15:10 +0000 |
|---|---|---|
| committer | Michael Witten <mfwitten@gmail.com> | 2011-08-02 21:34:37 +0000 |
| commit | 952df55b5a30913f4a5536b12ad09dd95c66d83f (patch) | |
| tree | 002cf986e3dfa770cf11e0aa376052eba6376774 /Documentation | |
| parent | e14bd7e614b57493e1cbefb8a06d3754bdd04e26 (diff) | |
| download | linux-952df55b5a30913f4a5536b12ad09dd95c66d83f.tar.gz | |
Docs: MSI-HOWTO: may -> might
Signed-off-by: Michael Witten <mfwitten@gmail.com>
Acked-by: Matthew Wilcox <matthew.r.wilcox@intel.com>
Signed-off-by: Randy Dunlap <rdunlap@xenotime.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/PCI/MSI-HOWTO.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/PCI/MSI-HOWTO.txt b/Documentation/PCI/MSI-HOWTO.txt index c9cffaf16f82..257628fdd464 100644 --- a/Documentation/PCI/MSI-HOWTO.txt +++ b/Documentation/PCI/MSI-HOWTO.txt @@ -250,7 +250,7 @@ the MSI-X facilities in preference to the MSI facilities. As mentioned above, MSI-X supports any number of interrupts between 1 and 2048. In constrast, MSI is restricted to a maximum of 32 interrupts (and must be a power of two). In addition, the MSI interrupt vectors must -be allocated consecutively, so the system may not be able to allocate +be allocated consecutively, so the system might not be able to allocate as many vectors for MSI as it could for MSI-X. On some platforms, MSI interrupts must all be targeted at the same set of CPUs whereas MSI-X interrupts can all be targeted at different CPUs. |