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| author | Tero Kristo <t-kristo@ti.com> | 2014-07-02 11:47:40 +0300 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-07-15 14:08:59 -0600 |
| commit | a24886e263ec4b7062c88cfa84577080ea00da94 (patch) | |
| tree | 57a4f018bac5132f4cfdaaa3194ea7a8e9664940 /arch/arm/mach-omap2/clock.c | |
| parent | 8111e01045c1b3ac6b5d3c2ee3b8dc562efdf3ae (diff) | |
| download | linux-a24886e263ec4b7062c88cfa84577080ea00da94.tar.gz | |
ARM: OMAP2+: clock: add fint values to the ti_clk_features struct
These are SoC specific and get their init values based on the SoC type.
Previously the values were hard coded within the DPLL clock code, but
having them inside the clock features avoids runtime cpu_is_X type checks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.c')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7897053ce676..7efe66e3a029 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -51,6 +51,19 @@ u16 cpu_mask; */ struct ti_clk_features ti_clk_features; +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 +#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 +#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 +#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 + +/* + * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. + * From device data manual section 4.3 "DPLL and DLL Specifications". + */ +#define OMAP3PLUS_DPLL_FINT_MIN 32000 +#define OMAP3PLUS_DPLL_FINT_MAX 52000000 + /* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock @@ -744,4 +757,14 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, */ void __init ti_clk_init_features(void) { + /* Fint setup for DPLLs */ + if (cpu_is_omap3430()) { + ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + } else { + ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + } } |