diff options
| author | Mike Leach <mike.leach@linaro.org> | 2017-02-17 19:13:10 +0000 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2017-02-21 16:02:02 +0000 |
| commit | 7e6a69ee954caf8dd8c98f70c8ee894c8ebfdcf0 (patch) | |
| tree | b7c8a1ad79334a7f3a31da428db8c855c2cf75f5 /arch/arm64/boot/dts/arm/juno-base.dtsi | |
| parent | 1492a864364ed46be2abeaaaf3b1a248f19e6644 (diff) | |
| download | linux-7e6a69ee954caf8dd8c98f70c8ee894c8ebfdcf0.tar.gz | |
arm64: dts: juno: update definition for programmable replicator
Juno platforms have a programmable replicator splitting the trace output
to TPIU and ETR. Currently this is not being programmed as it is being
treated as a none-programmable replicator - which is the default
operational mode for these devices. The TPIU in the system is enabled by
default, and this combination is causing back-pressure in the trace
system resulting in overflows at the source.
Replaces the existing definition with one that defines the programmable
replicator, using the "qcom,coresight-replicator1x" driver that provides
the correct functionality for CoreSight programmable replicators.
Reviewed-and-Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/juno-base.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-base.dtsi | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 9d799d938d2f..df539e865b90 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -372,12 +372,13 @@ }; }; - coresight-replicator { - /* - * Non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-replicator"; + replicator@20120000 { + compatible = "qcom,coresight-replicator1x", "arm,primecell"; + reg = <0 0x20120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; ports { #address-cells = <1>; |