diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-09 16:08:04 +0900 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-10-09 16:08:04 +0900 |
commit | de390bba797aa9a554bc1769b6a8771605854d79 (patch) | |
tree | ce95610d4a70ec0a7307a30cfd1a66fdf0c901ab /arch/mips/kernel/smp-mt.c | |
parent | 50e0d10232db05c6776afcf6098459bff47e8b15 (diff) | |
parent | 382fc33b4a04e2dde89b4c69a6880e0c7d9761e2 (diff) | |
download | linux-de390bba797aa9a554bc1769b6a8771605854d79.tar.gz |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle:
"This is the MIPS update for 3.7.
A fair chunk of them are platform updates to the Cavium Octeon SOC
(which involves machine generated header files of considerable size),
Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
platforms.
Support for the commercial MIPS simulator MIPSsim has been removed as
MIPS Technologies is shifting away from this product and Qemu is
offering various more powerful platforms. The generic MIPS code can
now also probe for no-execute / write-only TLB features implemented
without the full SmartMIPS extension as permitted by the latest MIPS
processor architecture. Lots of small changes to generic code."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
MIPS: BCM63XX: Properly handle mac address octet overflow
MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
MIPS: Replace `-' in defconfig filename wth `_' for consistency.
MIPS: Wire kcmp syscall.
MIPS: MIPSsim: Remove the MIPSsim platform.
MIPS: NOTIFY_RESUME is not needed in TIF masks
MIPS: Merge the identical "return from syscall" per-ABI code
MIPS: Unobfuscate _TIF..._MASK
MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
MIPS: Add base architecture support for RI and XI.
MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
MIPS: uasm: Add INS and EXT instructions.
MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
MIPS: Make VPE count to be one-based.
MIPS: Add new end of interrupt functionality for GIC.
MIPS: Add EIC support for GIC.
MIPS: Code clean-ups for the GIC.
...
Diffstat (limited to 'arch/mips/kernel/smp-mt.c')
-rw-r--r-- | arch/mips/kernel/smp-mt.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index ff17868734cf..2defa2bbdaa7 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -150,6 +150,7 @@ static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { +#ifdef CONFIG_IRQ_GIC extern int gic_present; /* This is Malta specific: IPI,performance and timer interrupts */ @@ -157,6 +158,7 @@ static void __cpuinit vsmp_init_secondary(void) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 | STATUSF_IP7); else +#endif change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7); } |