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authorChristoph Hellwig <hch@lst.de>2020-09-25 06:19:19 +0200
committerChristoph Hellwig <hch@lst.de>2020-09-25 06:19:19 +0200
commit8c1c6c7588b2faf9dd45fb3cfb7497fd09bbfe7c (patch)
tree50a7ddcfd7e7b1a7e4fb656bb88a036dbcff4bd6 /arch/mips/mm
parent38225f2ef2f4263fc65acae63fdd4e8489c9ffcf (diff)
parent171d4ff79f965c1f164705ef0aaea102a6ad238b (diff)
downloadlinux-8c1c6c7588b2faf9dd45fb3cfb7497fd09bbfe7c.tar.gz
Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into dma-mapping-for-next
Pull in the latest 5.9 tree for the commit to revert the V4L2_FLAG_MEMORY_NON_CONSISTENT uapi addition.
Diffstat (limited to 'arch/mips/mm')
-rw-r--r--arch/mips/mm/c-r4k.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index fc5a6d25f74f..0ef717093262 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1712,7 +1712,11 @@ static void setup_scache(void)
printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
scache_size >> 10,
way_string[c->scache.ways], c->scache.linesz);
+
+ if (current_cpu_type() == CPU_BMIPS5000)
+ c->options |= MIPS_CPU_INCLUSIVE_CACHES;
}
+
#else
if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
panic("Dunno how to handle MIPS32 / MIPS64 second level cache");